#milkymist IRC log for Thursday, 2013-05-16

lekerneldavidc__, yes it does not touch the PLL08:34
lekerneldavidc__, and HDMI is in 3.3V bank while SDRAM in a 2.5V one08:35
lekernelmaybe the problem is inside the FPGA, I don't know ...08:36
lekernelwpwrak, I'm using a rc2 board08:58
lekernelshouldn't make a difference, but of course sdram reads shouldn't mess with hdmi either08:59
wpwrakah, i see. maybe try in another board, just to make sure it's not some localized weirdness ?09:04
wpwrak(unlikely, but you never know)09:05
lekerneloh, the bug isn't there on rc312:14
lekernelor rather, much less marked12:14
lekernelat least to the point where I can make demos without apologizing. great.12:16
lekernelwpwrak, thanks for the good idea :)12:16
lekernelif I'm lucky it will work perfectly on the mixxeo, which will have proper differential pairs all the way to the fpga12:17
lekernelI'm still curious though... what the hell can cause something like that12:19
wpwrak(r3) probably depends on the phase of the moon, too ;-)12:20
lekernelwould be great to hear what happens on your board12:22
lekernelthere's a little rework - cut the high speed traces near the connector on the HDMI add-on, and insert a 24 ohm series resistor on each12:22
wpwrakdo i need to feed both HDMI channels ?12:23
lekernelthis appears to improves signal integrity - of course can't tell you exactly how much with the scope I have, but it makes ch B able to synchronize and greatly reduces the noise on the pictures12:23
lekernelno12:23
wpwrakdoes the SI issues affect ch A and ch B in the same way ?12:24
lekernelch B seems to be more affected, since you can't even sync without the resistors12:24
lekernelyou just get a pixel soup of your original picture12:25
lekernelbeing put in the blender :)12:25
lekernelif you don't want to connect the pots you can change the readout routine12:27
lekernelhttps://github.com/milkymist/milkymist-ng/blob/master/software/videomixer/main.c#L2812:27
lekernelotherwise the pot connection is TP20 -> charge, TP16 -> blackout, TP17 -> crossfade12:28
wpwrakhmm, no 24 Ohm in 0402. only 18 and 3312:30
wpwraki have 22 and 27 in 0603, though12:31
wpwrakcould stack 2 x 47, though12:32
wpwrakhow precise does it have to be ? also, how did you end up with 24 ?12:33
wpwraka quick look at rc2 vs. rc3 gerbers reveals nothing suspicious. vga traces cross ext conn traces, but you've already eliminated that. besides, there's a ground plane between them.12:38
wpwrakhmm, that rework will be tricky. i added pin headers on top if the solder side of the connector, so the whole area is difficult to access12:44
wpwraks/ if / of /12:44
wpwraklet's see if the pixel soup without resistors looks tasty12:45
lekernel(24) just tried random values13:03
lekernel10, 24, 33 and 5013:04
lekerneland 24 seemed to work the best13:04
lekerneluse the 22 ohm ones13:04
wpwraklet's try the soup view first13:08
wpwrak hmm, just updated mibuild and migen. the install complains about the "yield from" in file "/usr/local/lib/python3.2/dist-packages/migen-unknown-py3.2.egg/migen/genlib/record.py", line 9313:14
wpwrakis this just a typo or to i need a different version of python ?13:14
wpwrakoops, wrong channel. sorry.13:14
lekernel3.3 yes13:14
lekerneland then you may hit a Xst bug that gets it stuck at "Analyzing FSM xxx for best encoding"13:15
wpwrakphew. as if 3.2 wasn't bleeding edge enough ...13:15
lekernelyou can work it around with http://pastebin.com/XppJDu1w13:15
wpwrakso is this a change i should just make, or only if i run into trouble ?13:17
lekernel14.4 and 14.5 have the bug13:17
wpwrakhmm yes, 14.4 is what i have13:18
wpwrakinstalled python 3.3, migen still invokes python 3.213:22
wpwrakhttp://pastebin.com/N5G9Qk0E ?13:24
lekernelmigen doesn't invoke any python version13:24
lekernelah the install script13:24
lekernelI don't actually use it :)13:25
GitHub144[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/E4ppQQ13:26
GitHub144migen/master 27accd7 Sebastien Bourdeauducq: setup.py: update required Python version13:26
lekernelyou need a bios reflash for supporting the new timer too13:26
lekernelif you want to generate csr.h without waiting for ISE you can do build.py --no-run13:27
wpwrakanf the build instructions fgor milkymist-ng seem incomplete. i guess i need to build some libraries before i can "cd software/bios && make"13:28
lekerneldon't this makefile build the libs?13:28
lekernelit should... but of course, it's not like I have time to test all those details13:29
wpwrakmuch more efficient to have them reported one by one by people who don't actually know what's supposed to happen ;-)13:29
wpwrakthe setup.py change doesn't help. now  setup.py build  fails with Migen requires python 3.3 or greater13:30
wpwrakpython3 --version  =>  3.2.313:31
wpwrakso i guess you need to make the version explicit13:31
lekerneljust run python3.3 setup.py13:31
wpwrakor teach setup.py to look for a matching interpreter13:31
lekernel-ENOTIME13:31
lekernelenv python3.3 will fail with python 3.413:32
wpwraki would say "change the build instructions then" but there don't seem to be any :)13:33
wpwraklet's see .. i updated mibuild, migen ... now, to milkymist-ng13:34
lekernelwell now it clearly says you need python 3.3+, which is good enough, no need to waste more time on this trivial detail13:34
wpwrak"but i have it installed" ;-)13:35
wpwrakah, something made the dependencies now. funny. maybe it was the csrs, not the library13:40
lekernelinterestingly, I have a perfectly still picture by increasing the clock frequency to 75MHz - even though ISE claims the timing isn't met. my first thought, of course, was that it had crashed ;)13:42
lekernelwell almost perfectly still ...13:43
lekernelbut that's a different bug than the garbled signal during SDRAM reads on my other board13:43
wpwrakin other news, xilinx are now hiring alchemists for their hard sciences department :)13:44
lekernelit could be that the HDMI pixel FIFO overflows sometimes13:44
wpwrakmaybe indicate fifo overflow on a led ?13:45
lekernelbut that doesn't affect the line counter, which shows the SDRAM read bug on the other board13:45
wpwrak i wonder if we can add a termination in the FPGA for the pixel clock23:51
--- Fri May 17 201300:00

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