#milkymist IRC log for Tuesday, 2013-05-14

--- Tue May 14 201300:00
Fallenou_lekernel: about the 700 EUR/board, the M1R4 bom seems to be ~ $212 , so all the remaining is PCB price?12:32
Fallenou_that's expensive isn't it?12:32
Fallenou_pcb + mounting components12:33
lekernelthat's for 6 pcs12:35
wpwrakpcb and smt usually have significant fixed costs. so if the number of units is low, each has to cover a large share of that12:35
lekernelincluding pcb and assembly12:35
wpwrakFallenou_: also, you have yield to consider. you can't expect 100% of all boards to just work. some may need minor fixing, some may just be writeoffs12:36
wpwraklekernel: so to get 6, you'd fab at least 8, right ?12:36
lekernelI fab 6 + number of preorders... it's not *that* bad, all 5 first M1 we made worked in the end, after rework12:37
larscI think I'll take one12:39
wpwrakdepends on how good your fab is ... for a first run, you shouldn't expect > 95% yield for this kind of board12:40
wpwrakfor comparison, atben had 100%, atusb had about 97.7%12:41
lekernelfrom what I have seen and the "samples" I have on my desk, they seem pretty good12:42
lekernelthey also noticed immediately the M1 PCB Altium files were a messed up PADS conversion... ahem12:43
wpwrak;-) did you get the original files from wolfgang ?12:45
lekernelno12:45
wpwrak:-(12:45
wpwrakso what will you do ?12:45
wpwrakswitch to kicad ? :)12:45
lekernelemail went to the trap, so I'm paying them extra for fixing the altium files12:45
wpwrakargh12:45
wpwrakthis seems like the perfect moment to leave the ugly world of proprietary tools and formats behind.12:46
wpwrakwhat you're doing now is basically paying to get your prison cell repainted ...12:47
lekernelin a couple years the slowtan6 will be completely obsolete, and then I'll have to redo a complete board anyway12:48
lekernelhopefully kicad will have improved by then12:48
lekernel*that* would be the perfect moment to switch12:49
wpwrakkicad is constantly improving. what you're saying sounds a bit like "oh, i won't buy a PC just now. i'll rather wait until the technology is mature and doesn't change all the time."12:53
lekernelexcept that the extra is a lot less than a complete redesign12:53
lekernelright now I just want to have a first version out to get market feedback asap - can be a tougher beast than most technical problems12:54
wpwrakwe're kinda 60% there when it comes to a redesign. we have compelete schematics in kicad, most of the footprints, all that's missing is the layout12:57
Fallenou_layout is not the easiest thing :)13:00
wpwrakthat's why i allocate a generous 40% :)13:06
wpwrakwe already have: 1) high-level design (with component selection, all sorts of calculations, etc.), 2) schematics symbols, 3) schematics, 4) schematics review, 5) most of the footprints13:07
wpwrakfor mixxeo, we'd need to redo part of the schematics, but it would be mainly an exercise in copy and trim. so relatively little new work.13:08
wpwrakand yes, it's still a lot. but unless you ride out and slay that darn dragon, the villagers will always live in fear :)13:09
lekernelright, and then we fab that, then the SDRAM doesn't work because of SI, and then what?13:09
lekernelcan kicad even route differential pairs for the HDMI?13:10
wpwrakyes, you have to expect one failed run13:10
lekernelin any other way than manually?13:10
wpwrakdepends on the skills of the one doing the routing :)13:10
wpwrakafaik, there still no autorouting i'd want to use. there's an external non-open router, though13:11
wpwrakwhat i do when i need some feature that's not in kicad is usually to write an external tool that provides it for me. that tends to be easier than mess with C++ and GUI. so for differential traces, i'd make a tool that calculates the length of a given net (selected by name)13:12
wpwrakadd a "compare and complain if delta > X" mode and you have a nicely automated sanity checking pass13:13
lekernelnot quite the "get the goddamn board out asap" way13:17
wpwrakyes, but you'll always have that problem. sometimes, you have to invest a bit into the future.13:18
lekernelI'll do that when I have a good reason, such as switching to a better fpga13:18
lekernelcombined with real demand for the device13:19
wpwrakyeah, let's see how this goes13:23
wpwrakyour announcement is a little obscure, so unless you want to limit this to people who already follow your day to day work, you may want to explain this in a bit more detail. also, are you sure everyone understands what a "Slowtan6" is ? :)13:25
Action: Fallenou_ agrees13:26
lekernelsince this is a first "for-developers" prototype, the audience is still quite limited for now, yes... what points are obscure?13:28
Fallenou_well, if we want to diminish the price (and then have more people involved and then diminish the price etc etc) we need more people buying it, and then a good explanation of what it is, what it can/could do13:29
Fallenou_what's the goal of the device13:29
Fallenou_what's on it/ not on it13:29
Fallenou_etc13:29
Fallenou_maybe a picture, a video of you using it13:29
Fallenou_something that helps convince someone to buy one13:29
Fallenou_if I get the dual dvi pcb one day, I could try doing such a video13:30
Fallenou_(the one you sent to Alarm)13:30
Fallenou_I will try to arrange a meeting with him about the assembly13:30
lekernelsure, but that's coming later...13:35
lekernelalong with a case, complete with built in controls, etc.13:36
lekernelI just need that proto to move forward with the development13:36
wpwrak(obscure) the slowtan, for example. also, the purpose of the board isn't quite clear. is it intended only for co-developing the HDMI mixer ? does it have uses independent from what you're doing ?13:36
lekernelI think most FPGA developers understand "slowtan" ;)13:36
Fallenou_=)13:37
wpwrakalso, the user interface is a unclear. does "no knobs" mean that the pots are there, just without knobs on them ? or if not, are the adcs ?13:37
lekernelit's just bare FPGA IO - we may want optical pots instead, still undecided13:38
wpwrakin most languages "slowtan" sounds structurally different from "spartan". so even if you're very familiar with the chip family's slowness, it's a bit of a leap13:39
wpwrakbesides, it's already included in "spartan": "practicing great self-denial"13:39
wpwrakmaybe you could make a diagram of things that you'll include and things the user would typically add. that way, you can show the overall concept but also make clear what parts are left out.13:40
wpwrakactually, dict is great. under "spartan": "do something for no other reason than that you would rather not do it" -- William James13:42
wpwraksomewhat surprisingly, the thesaurus doesn't make the connection to "masochistic", though13:43
larscfrom fpga-developer?13:47
lekernelyes and I want to develop the product/design/UI aspects with people who have good experience with that, who aren't on the MM list yet, and I'm leaving those out of the first proto phase purposefully13:50
lekernels/those/those aspects/13:51
lekernelso that's why there is just a bare FPGA IO connector, without pots (how many? what type? where? I don't know yet), screen(s), etc.13:52
larscthere is still ethernet right?13:52
lekernelfor now yes13:52
wpwrakpity that you're scrapping USB. there's a ton of USB-MIDI equipment with all sorts of pots and such you could use. well, you can still do it over ethernet, with a laptop acting as gateway.13:53
lekernelI still want to be able to pull off TFTP transfers if the HDMI decoder is giving me trouble again13:53
lekerneljust put that on the IO connectors13:53
lekerneland there is still no good USB software, and debugging USB is a major PITA as I have discovered13:54
larscpop quiz - which website is he talking about: "The only reason I'm slightly reticent is that they're website is rather nasty. It feels like it's run by a company, and projects just get shoved in a big list."13:54
wpwraklarsc: too many sites ? :)13:54
larscit's somewhat on topic13:55
wpwrakmust be opencores13:55
larschehe13:55
wpwrakat least that's the impression i vaguely recall getting when i briefly looked at it some years ago. haven't paid much attention to it since :)13:56
Fallenou_lekernel: even if it's a pain, work has been done so that some stuff work (usb midi14:08
Fallenou_I imagine you don't care about mouse and keyboard anymore14:09
Fallenou_but usb midi is really cool/nice/useful14:09
Fallenou_I really enjoyed the M1 + USB midi experience when I tried14:09
Fallenou_using the nanoKontroller14:09
Fallenou_I think it was the most fun I had with it :)14:09
lekernelit'll be a support and UI pain... maybe as an unsupported hacker extension14:11
lekernelthe mouse I bought 2 months ago, for example, still tickles M1 USB bugs. oh well...14:11
Fallenou_well, you don't have to give support, you say USB is there for those who want to spend their time figuring out how it works on their own14:12
lekernelI have a different way of doing things now14:12
lekernelany connector protruding out of the case must work perfectly14:12
Fallenou_but it can be nice to have it, since some device already work *today* without hacks14:12
Fallenou_hum ok14:12
Fallenou_if there is an expansion port where I can plug a "usb daughter board" then it's OK I guess :)14:13
lekernelthere is, but my involvement is pretty much reviewing patches and merging those that don't introduce any regression into the codebase14:15
wpwrakyou could design the board such that you can mount daughterboards as "bridges" over the main circuit14:15
wpwraklater on, add a split sidewall and you can have make custom covers with relative ease.14:16
wpwraks/have make/make/14:16
wpwrakkicad now has python scripting support in pcbnew. that ought to help with things like differential lines14:21
lekernelI hear you wpwrak14:23
lekernelnext board with kintex-7 I'll give it a try...14:23
wpwrak(just thinking aloud while catching up with the last few months of the kicad lists :)14:31
wpwraklekernel: actually, since you're already making a PCB + SMT run, that would be a good moment to sneak in a a kicad-based board design. should be much cheaper than setting up a separate run. and the BOM is identical anyway.20:44
lekernelthe problem is the cost of making the kicad design in the first place, plus the risk of getting things wrong as opposed to basing on the already tested M1 layout20:46
lekernelas you noted, those boards are expensive, so I really want to avoid respins20:47
lekerneland how would you "sneak" another design? you have to redo PCB masks, stencils, reprogram the pick and place machine, etc.20:48
lekerneland that's where the money is going20:49
wpwrakyou panelize the PCB anyway, so instead of one panel with N PADS-based designs, you have one with N-1 PADS plus one kicad20:53
wpwrakthe P&P, yes, you need an extra set of positions. but you don;t need to load new parts. so that should be a lot cheaper.20:54
wpwrakand yes, you can't avoid the risk per se, or the cost of making the conversion. i suggested a saving, not a free lunch ;-)20:55
lekernelstill sounds like a lot of hassle20:56
lekernelI'd rather focus on, say, make a good pixel shader architecture :-)20:56
lekernelPCB and stuff like that, people take for granted20:57
lekerneldebugging USB is in the same category20:57
wpwrak;-) i was more thinking of it in term of finally liberating yourself from proprietary tools and file formats20:57
lekernelnext board20:58
lekerneland aren't panelized boards all exposed from the same mask anyway?20:59
lekernelI saw only one mask for the M1 ...20:59
wpwraki don't know how they expose the panelized board. i would have thought they make a board-sized mask. actually, i'm not even sure if they still make a mask nowadays or if they just plot directly on the board21:00
lekernelthe M1 had masks21:01
wpwrakthere are companies that aggregate multiple designs on a single PCB, to keep the cost low. that would suggest that there is considerable saving in doing that.21:02
wpwrakbut perhaps you can ask them how the price calculation would change.21:02
wpwrakalso, those recovered PADS files, will they actually be fully editable, with DRC information and all that ? because if they aren't you'll have just the same set of troubles if you make another board revision.21:10
lekernelnothing will be in PADS anymore21:18
lekernelthey take the current altium file converted from PADS and fix the problems that the conversion introduced21:18
lekernelthen we can forget about PADS21:18
wpwrakso you'll have fully editable altium ?21:21
lekernelthe big bad wolf ate the original PADS files anyway21:22
lekernelyes21:22
wpwrakmust be why he seems so sleepy now ;-)21:23
lekerneland edited to add HDMI etc.21:23
lekernelin altium21:23
wpwrakhmm. i'm kinda curious how that will go. i'm rather sceptical about conversions between complex formats.21:25
lekernelwell the PCB guy seemed pretty sure of himself...21:34
wpwrakyeah. it's rather interesting that botched PADS conversions would be "business as usual" for a PCB house :)21:35
davidc___lekernel: if you want me to look at the altium files / fix anything up, I have a full Altium license21:52
wpwrakhmm, rules for differential traces: roughly the same length for sure. then i think it already gets design-specific. constant distance from each other ? bend radius ? what happens if the circuit is asymmetric, e.g., one has a test point added, either in-line or with a T trace ?22:06
wpwrakthen, how do vias enter the equation. let's say the + trace has to cross the - trace, so one goes under the other. does the length then become len(layer1)+len(layer2)+2*Z(layer1, layer2) ?22:07
wpwrakthen, one output, two inputs, so you get a Y. let's call the output A, the inputs B and C, and the branching point Y. is the rule (A+B+) == (A-B-) && (A+C+) == (A-C-) or do also the AY have to match ?22:09
davidc___wpwrak: you can't really do a 'Y' with a diff pair22:13
davidc___wpwrak: [well, unless you do controlled impedance tricks and your receivers don't care about the halved amplitude]22:13
davidc___wpwrak: or you double the characteristic impedance + termination on each leg of the Y22:14
wpwraki mean splitting + and -. that should still give you the full amplitude.22:14
wpwrakwell, almost full. not sure how much the termination eats.22:16
davidc___wpwrak: simulate it in a spice that supports transmission lines; you'll be horrified by the output waveform ;)22:17
wpwrak;-)22:18
wpwrakso you're saying this sort of topology is something i don't have to worry about. good. that simplifies things :)22:19
wpwraki guess the T would be similar. if the T was normally unterminated (i.e., just for probing), would the test point be in-line or with a short trace branching off the (half-pair) differential line ?22:21
davidc___The T is troublesome reflection-wise [if unterminated]22:22
wpwrakalso if inline ?22:22
davidc___depends on your probe. and your rise time :)22:23
wpwrakyeah :)22:23
wpwrakso you're saying it's either don't care or it becomes another Y, which we've already elimiated22:23
wpwrakexcellent. killing all the oddball cases helps :)22:23
davidc___wpwrak: well; if your probe input impedance is 1Mohm, then thats OK :)22:23
wpwrakthe probe would usually be high-Z, yes22:24
davidc___wpwrak: I'll try and dig out my SI books tonight + recommend you some [or some PDFs ;)]22:24
wpwrakany intuition about the X ?22:24
wpwrak(+ and - crossing)22:25
wpwrakapart from probably being undesirable. but sometimes you have no choice22:25
davidc___oh that? Eh, it'll introduce a slight discontinuity22:25
davidc___Also, how well you need to length match depends on your driver rise-time. You might have tons of skew to play with depending on what you're using22:26
wpwrakyup, that's clear (limit on how precisely you have to match the length)22:27
wpwrakthe discontinuity ... you mean length ? or reflections (from trace-via-trace-via-trace)22:27
davidc___wpwrak: impedance discontinuity causing reflections.. Anyhow - what are you trying to route?22:28
davidc___wpwrak: [also, lots of diff standards; especially when running into an FPGA, can just be inverted]. PCIE for example allows inversion for easier routing22:28
davidc___and you can just flip it in FPGA logic22:28
wpwraki'm trying to come up with a set of things you have to know to handle common differential configurations22:29
wpwraki.e., is it usually sufficient to know the total length of the net ? or do you need the lengths of all paths ? etc.22:29
wpwrakif T and Y are to be avoided, the total net seems to be sufficient22:29
davidc___wpwrak: ideally, total-length-of-net should be end-to-end length22:29
wpwrakyup. with Y and T gone, it's the same :)22:30
davidc___wpwrak: they don't _need_ to be avoided; it just falls into the "you better check your work" category ;)22:30
wpwrak(inversion) ah, interesting22:30
davidc___wpwrak: check out http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=6d37ec2f8543fc1f9d8ace6264d08b469f57e5f122:31
davidc___wpwrak: seems to be accurate and contain good tricks22:31
wpwrakPCI express serial differential makes things too easy ;-)22:33
davidc___wpwrak: I laid out a PCI bus.... In eagle. [and back in the ancient days of eagle too]22:33
davidc___It was not fun.22:33
davidc___Worked first time though [I was anal about matching everything]22:33
wpwraka board with the proper amount of serpentines has a certain arcane touch to it :)22:34
wpwraktest pads in line ... good22:39
davidc___wpwrak: check out http://www.pcbcarolina.com/images/Presentation_-_Hartley_-_Diff_Pairs.pdf as well. Seems to be accurate [based on what I remember]22:39
davidc___and also talks about skew budgets / etc22:39
wpwrakheh, page 2 ;-)22:41
davidc___And its corrolary - "Anything said by Xilinx should be assumed to be a lie; unless proven by volume-purchasable, working hardware"22:43
wpwrakyeha, xilinx seem to be pretty close to the bleeding edge :)22:43
wpwraki wonder how altera, lattice, etc., are doing in that regard22:43
wpwrakinteresting math for the trace widths and separation22:48
wpwraki wonder if there's a calculator for that somewhere22:48
wpwrak(open source, of course)22:48
davidc___wpwrak: There are, but there are a ton of formulae that disagree. I've used some of the Polar products before and had good results at MFG time22:49
davidc___wpwrak: really; talk to your board fab :)22:49
wpwrakgrmbl :)22:49
davidc___wpwrak: What kind of signals are you trying to route?22:49
davidc___wpwrak: because for short-enough runs at slow-enough risetimes, it just doesnt matter22:50
wpwrakthe question i'm trying to answer is "what is the minimum set of features that should be put into or around kicad in order to be able to usefully route differential signals ?"22:50
wpwrakso yes, my conclusion so far is that it gets very very complex when working with very high speeds, etc.22:51
davidc___Oh, gotcha. Yeah, start with just "draw two lines in parallel at a specified spacing"22:51
davidc___That takes care of 90% of the pain.22:52
wpwrakwhile for more relaxed (and hopefully more common for a while) cases, little more than parallelism and perhaps rough length matching would be needed22:52
davidc___The rest can be tweaked by hand; especially if there is a net query tool22:52
davidc___[better yet, the ability to have a DRC rule that says abs(len(x) - len(y)) shall not exceed n22:53
wpwraknet query = length ?22:53
davidc___yeah, sorry. I haven't used KiCAD in a long time22:53
wpwrakhaving it in DRC would be great. just having it available for manual checking may already be useful enough in many cases22:54
wpwrakgood. so my initial assumption that measuring the length of a net is the main item we need still stands.22:54
wpwraknow, let's see if they've added something like this since the last time i checked ...22:55
wpwrakbesides, length is also useful for synchronous buses, differential or not22:56
wpwrake.g., for making the serpentines not only visually pleasing :)22:56
wpwrakokay, we have track length. that's the same as net length in the point-to-point case23:15
--- Wed May 15 201300:00

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