| GitHub27 | [milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/eHQo-Q | 13:09 |
|---|---|---|
| GitHub27 | milkymist-ng/master 9c0d13b Sebastien Bourdeauducq: tb: add chansync | 13:09 |
| GitHub27 | milkymist-ng/master d05f3d2 Sebastien Bourdeauducq: chansync: bugfix | 13:09 |
| lekernel | seriously, swapping two completely regular synchronous signals between logic results in | 19:19 |
| lekernel | WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the | 19:19 |
| lekernel | rest of the | 19:19 |
| lekernel | design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints. | 19:19 |
| lekernel | To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: | 19:19 |
| lekernel | Unroutable signal: m1crg/pllout4 pin: m1crg/vga_clock_gen/CLKIN | 19:19 |
| lekernel | ISE is such a pile of shit | 19:20 |
| larsc | yep | 19:20 |
| lekernel | alright... let's unswap the signals, wait 15min, run the windu and motif based fpga editor bloatware, lock all suspicious components, swap the signals back, wait 15min, and try again ... | 19:24 |
| lekernel | ah, I forgot the "instance not found" error cycles with a 5-minute wait before you can find what funny name Xst has made up for all of them | 19:25 |
| lekernel | yay, got color and only slightly buggy FPGA decoding! | 19:55 |
| larsc | nice | 19:56 |
| Fallenou_ | \o/ | 20:01 |
| lekernel | xdl is actually a bit less annoying to use than fpga editor for looking at instance placements | 21:03 |
| lekernel | xdl -ncd2xdl top-routed.ncd then grep for the instance you're looking for | 21:06 |
| GitHub198 | [milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/DUzouw | 21:10 |
| GitHub198 | milkymist-ng/master 11cbdf0 Sebastien Bourdeauducq: build.py: support single DVI sampler | 21:10 |
| GitHub198 | milkymist-ng/master 784e96b Sebastien Bourdeauducq: build.py: LOC clock generator components to limit breakage of the ISE shitware | 21:10 |
| Fallenou_ | a shame you need to lock components | 21:14 |
| lekernel | it doesn't even work!!! wtf | 21:15 |
| lekernel | it still gives me this "unroutable" bullshit when changing some constants (!) in the code... | 21:15 |
| Fallenou_ | -_- | 21:15 |
| lekernel | with the same signals, and the LOCed components at the locations that worked just before | 21:16 |
| lekernel | well, I suppose multicore machines are for running multiple copies of the ISE shitware with different PRNG seeds, hoping that at least one will not display some stupid error message and will meet timing | 21:17 |
| Fallenou_ | hum did you lock the PRNG seed ? | 21:19 |
| Fallenou_ | ah you said that | 21:19 |
| lekernel | the most expensive Vivado license is $5795, wow ;) | 21:20 |
| lekernel | I guess someone has to pay the tech support salaries ... | 21:20 |
| Fallenou_ | ;) | 21:22 |
| Fallenou_ | gn8 ! | 21:24 |
| --- Mon May 6 2013 | 00:00 | |
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