#milkymist IRC log for Thursday, 2013-04-18

wpwrakinteresting ... my registers do actually seem to be present, but at weird places01:34
wpwrakokay, csr.h is just nonsense. nice trap :)01:56
wpwrakwhy oh why did it steal the "and" ?03:59
larscyou can't use 'and'06:09
larscuse &06:09
wpwrakGAAH ! use some pins of mmc.dat[] as output and migen makes ALL of them outputs, even if others are used only as input.06:09
wpwrak(and) migen is full of traps ...06:10
wpwraki now used a double If. that works :)06:10
larscalso & has higher precedence than !=06:10
wpwrakhence "and" :)06:12
larscwe can't overload and06:12
wpwrakrm -f *.py; vi syntax.y06:13
sb0wpwrak, (all outputs) what should it do instead? display an error?08:10
sb0or split the vector between inputs and outputs? my days are only 24h and already eaten by stupid bugs like in the hdmi stuff...08:11
wpwraksb0: yes, splitting everything into single bits would probably the best idea. it seems that, as soon as you use an aggregate - especially an array - bad things happen12:03
wpwraksb0: and bugs are just a part of life ;-)12:13
sb0wpwrak, how do you implement arithmetic if you only have single bits in verilog?13:50
sb0also splitting everything into single bits will produce ugly code13:51
sb0the verilog should still be human readable to some extent13:52
sb0so you really only want to split when 1) the signal is an IO and 2) has bits with different directions13:52
wpwrakin the most general case, you'd combine the single bits into a longer vector for access/operation14:17
wpwrakit should then be relatively straightforward to add a peephole "optimizer" that combines things where possible14:18
wpwrakin this case, the problem comes from migen's heuristics (generation of verilog declarations) going wrong. a contributing issue is that i think you don't really try to have a full semantical representation in migen, so migen doesn't even "know" something is wrong14:19
sb0no, it's really just a verilog IO problem14:26
sb0multi bit Signal == hardware integer == multi-bit verilog reg/wire14:26
sb0actually, instead of splitting, I think using "inout" as IO port declaration could also work14:27
wpwrakbtw, in my ADC, the check for termination isn't so nice. structurally, the test for termination should be in the busy.re Else branch. but i'm not sure how that would be done in migen (without making too much of a mess)14:27
sb0if the synthesizer does the right thing and doesn't try to mess with tri-state IO buffers14:28
wpwrakheh ;-)14:28
wpwrakthe thing is that in verilog, you explicitly declare what an aggregate is. so it's clear that it all is input or output14:29
sb0in migen too14:29
sb0Signal() is an aggregate14:29
wpwrakin migen, the declaration is implicit. so it's natural to assume the usual rules apply14:29
sb0no it's not14:29
sb0it's only "implicit" in the sense that mibuild returns you a multi bit signal when you have vectored pins14:30
wpwrakin Pyton, array elements are just like individual variables. the element doesn't "feel" it's part of an aggregate14:30
sb0it's not an array element14:30
sb0another solution is to make mibuild return a python list of 1-bit signals when there are vectored pins14:31
wpwraklook, feel, and smell are the same :) just the failure patterns differ14:31
wpwrakyes, i think the basic unit in migen should be the single bit, not the aggregate14:32
sb0then you get ugly generated verilog and messy arithmetic14:32
sb0just to solve an IO problem, come on14:32
sb0multi bit signals are great14:32
wpwrakyou can have the aggregate as a "hint" (e.g., bus[2] having attributes .parent_array = bus and .array_index = 2, or whatever). then the peephole optimizer could make an educated guess and produce more readable expressions. the semantics would be identical, though14:33
sb0try inout14:34
wpwrakso that's when you rewire the parameter passing logic ? (Instances, etc.) i thought migen was about making things simpler :)14:38
sb0?14:38
wpwrakanyway, the ADC works as it is. luckily, i eventually found a combination where the default end up right14:38
sb0no, I'm just saying that verilog may not whine anymore when you have a vectored port with differing directions declared as inout14:38
wpwrakand the way to declare that would be via Instance.Inout ? that's the only mention of "inout" i found in the manual14:39
sb0no, the verilog "inout" keyword14:39
wpwrakso i should patch top.v ?14:40
sb0instead of input/output. nothing to do with instances14:40
sb0yes try that first and then inout should be selected automatically when there is this problematic use of vectored signals14:40
sb0bbl14:41
wpwrakhackish :)14:42
--- Fri Apr 19 201300:00

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