| GitHub114 | [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/tknZ1w | 08:47 |
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| GitHub114 | milkymist-ng/master b018fce Sebastien Bourdeauducq: dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time | 08:47 |
| playthatbeat | my m1 is still displaying the patch name if i hit F1 in a performance.. anyone know why? | 16:52 |
| playthatbeat | oh, also: keyboard bindings don't work.. maybe related? | 16:55 |
| Fallenou | :q | 17:17 |
| wpwrak | hmm, can I access CSRs with mr and mw using the addresses in software/include/hw/csr.h ? | 23:20 |
| wpwrak | (CSRs) the ones i get with self.... = CSR() | 23:21 |
| wpwrak | for example, i have: self._r_polarity = CSR(2) self.comb += self._r_polarity.w.eq(polarity | 2) | 23:22 |
| wpwrak | counteradc_polarity_read says return MMPTR(0xe0006014) | 23:22 |
| wpwrak | mr 0xe0006014 yields 0xe0006014 00 00 00 00 | 23:22 |
| wpwrak | in top.py, i added my "counteradc" to csr_map and i assign the module as a submodule: self.submodules.counteradc = CounterADC(...) right after self.submodules.dvisampler1 = ... | 23:25 |
| wpwrak | i find the item i use in the verilog, so at a first glance, all looks sane | 23:27 |
| --- Thu Apr 18 2013 | 00:00 | |
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