#milkymist IRC log for Monday, 2013-04-15

_florent_hi12:57
_florent_it seems that current version of Migen does not implement slicing a slice for a signal12:57
_florent_with the current example, the generated verilog code is not correct: http://pastebin.com/crNyrn2U12:58
_florent_it returns that: http://pastebin.com/prAR5b9Q12:58
_florent_I find it can be very useful to support that it allows for example to pass a slice to a function or module and use slice into it.12:59
_florent_here is a dirty workaround I've implemented that seems to work: http://git.io/R6EPhw12:59
larscand verilog doesn't allow a slice of a slice?13:02
Fallenou_florent_: to avoid your migen api to be broken and be forced to update your verilog github repos, you can add migen as a git submodule inside your github projects13:05
Fallenouso that you can say "I want to use this Migen SHA-1"13:05
Fallenouand when you feel like it, you can update Migen SHA-1 and make the according changes in your code to update to the new API13:06
Fallenouthen your code is never "broken" by an update of your dependency13:06
lekernel_florent_, there are more cases where it would not work13:12
lekernelI think a good way to solve it is whenever you are not slicing a signal directly, create an intermediate signal and assign it the value to be sliced, and then slice that intermediate signal13:13
lekernelthat can be done easily using fhdl.visit.NodeTransformer13:13
lekernelverilog is really annoying sometimes13:14
_florent_fallenou: in fact I'm using my Migen fork13:16
lekerneld[64:1][32:1][16:1] can have clear semantics, I don't understand why it's not allowed13:16
Fallenou_florent_: ok, but someone cloning your github repos could not know that, could it ?13:16
lekerneldo parentheses help? (iirc no, but let's check)13:17
_florent_Ifallenou: yes I have to describe it in my projects13:17
lekernelthe 'assign to slice' case is more problematic too, so it would be great if parentheses worked13:17
Fallenou_florent_: yes that's a good alternative to using git submodules :) sometimes it can be a pain to use ... but I'm used to it now so I may have a compulsive need for it now :p13:19
Fallenoutime to see someone!13:20
_florent_lekernel: ok thanks, I'm going to check the parentheses13:21
wpwraklekernel: the problem with exposing verilog restrictions at the migen language level is that you destroy the nice abstraction migen aims to provide13:21
lekernelI'm not arguing that this should not be fixed - it should13:21
wpwrakgood :)13:22
lekernelchoosing the always@* form + reset when only slices of the signal are assigned should be done too (and would fix your bitgen problem)13:24
_florent_hmm..parentheses don't seems to work with verilog..13:26
lekernelyeh that's what I thought...13:26
lekernelso for reading slices, the temporary signal solution is easy enough13:27
_florent_ok I will have a look at NodeTransformer13:28
lekernelfor writing slices, I think you have to handle messes like {{a[3:4], b, {c, d[30:10]}[4]}, e}[10:0] <= some_value13:28
lekernelmaybe by also storing some_value in an intermediary signal, then dissecting the mess and assign a slice of some_value to a, b, ... and/or e individually13:29
wpwrakyeah, i think you need to process the semantical structure of such expressions. it's not just a matter of substituting text13:31
_florent_is it already possible to slice a Cat like this: c.eq(Cat(a, b)[10:0])?13:54
lekernelno13:54
lekernelit will output {b, a}[10:0]13:55
wpwrak_florent_: what a cruel thought ! slicing a poor little kitten ...13:55
lekernelwhich verilog doesn't like13:55
_florent_ok, it will be needed if you want {{a[3:4], b, {c, d[30:10]}[4]}, e}[10:0] to be working13:55
lekernelslice are the other way around in migen (like python) btw13:55
lekernelso you probably mean  c.eq(Cat(a, b)[0:10]) and you can also write [:10]13:56
_florent_yes sorry, I'm aware of that, juste mixing langage...13:56
_florent_just13:56
wpwraklekernel: it may help to clarify things if you'd make a drawing in the manual. your description needs a lot of context to make sense.13:57
lekernelthe only case which is implemented correctly now is directly slicing a signal13:57
lekernelthere are bugs in all other cases13:57
_florent_maybe it's not useful to support all the others cases13:58
lekernelI think it is useful to some degree13:58
lekernelnot only to have a clean abstraction, but there are also practical cases where it's useful13:59
lekernelbut I'd agree they are a minority of cases13:59
wpwrakand it helps to make programs more readable13:59
wpwraka language that has all sorts of quirks and exceptions very quickly becomes a playground for voodoo programming14:00
wpwrakbut then, i think migen may be an interim solution. a way to gather experience with a "better" HDL. at some point in time, you may decide to make changes to the syntax that exceed what you can do in python, and either make some sort of preprocessor/precompiler, much like you're hiding ISE now, or even make your own language without translating to python14:04
_florent_at least even it's not implemented, Migen should raise an "NotImplemented Error" instead of generating incorrect verilog code.14:04
_florent_but it's maybe not easy to cover all theses cases14:05
lekernelJFII14:07
wpwraki think when you're able to detect it, you could probably just support it as the programmer intends :)14:08
lekernelyes :)14:08
lekernel_florent_, what would you think about changing the Migen license to BSD?14:23
lekernellarsc azonenberg14:25
larsclekernel: yes please!14:28
larscwould allow me to use it at work14:29
_florent_same for me, I will be able to use it for my customers or the will be able to use if directly14:31
_florent_*they14:31
Fallenoubsd powa :)14:37
wpwrakin general, picking one of the "standard" licenses is vastly preferable over a homegrown or bastardized license14:41
lekernelyay, my customer likes my "top-notch-MBE lab time accepted as payment" quote15:09
lekernellet's first redefine what "DIY LED blinker" means, then do something useful like single photon avalanche diodes ...15:10
Action: lekernel needs a second life15:10
wpwrakMolecular Beam Epitaxy ?15:16
wpwrakand you told them you need that to blink LEDs ? :)15:16
Fallenounice so you eventually have access to such "toys" :)15:19
Fallenoulet's make transistors!15:20
Fallenoulet's make Milkymist SoC asics with MBE!15:20
lekernelI'm not sure if they can do complex patterns for eg CPUs...15:20
lekerneland I'd start with a 6502 instead, which already has well known and well tested masks15:21
lekernelor a 400415:21
lekernelthe avalanche diodes I'm pretty sure they can make them, and quantum physics experiments at home are cool too15:23
wpwrakand long as you don't find a low-energy way to produce black holes or strange matter ... :)15:28
lekernelI should also find a lab that has good CVD machines (they don't have any) and then try to run a "make your own diamond from pencil lead material" workshop at some future EHSM ;)15:29
lekernelhttp://en.wikipedia.org/wiki/File:Apollo_synthetic_diamond.jpg15:29
lekernelnote sure you can use actual pencil leads though. they probably have lots of contaminants...15:30
wpwraklekernel: so .. how's the issues situation now ? you said the clock is stable ?15:52
wpwrakregarding your failing channel B, could it be a problem with the HPD resistor ? (R27)15:53
lekernelwell the PLL never loses lock anymore, even with resolutions higher than 640x480 60Hz15:54
lekernelbut there's still a whole circus of bugs after that... no further improvement at all15:55
lekernelso I'll stick with the plan of sending raw data to DRAM15:55
lekerneland check I don15:55
lekernel't just try to process garbage15:56
lekernelhaven't looked at the ch B issue yet15:56
wpwrakwhat may also help is to try to decode the frame structure and output frames on VGA. that way, you may be see at one glance how things are wrong, particularly when problems are somewhat infrequent15:57
lekernelnon-problems are somewhat infrequent :) for example a horizontal pixel counter displays "640" in something like 2% of the cases, and some random values 98% of the time15:58
wpwrakyou can now calculate the statistical probability of just randomly picking 640 ;-)15:59
lekerneland that's when disabling inter channel synchronization... absolutely nothing works when it's enabled15:59
wpwrakwell, start with one channel ...15:59
lekernelwell it's statistically significant I think ;)15:59
lekerneland I constantly have to deal with ISE breakage all the time, this stuff is really frustrating16:00
lekerneland of course, breakage only after those 15 minutes of compilation...16:02
wpwrakthey should switch to code generation bugs that are activated at run-time, with a delay timer. that way, it'll take even longer to find them16:03
lekerneloh, it happens too...16:05
lekernelon the M401, ISE was generating subltly broken code for LM32 that let all sort of software running correctly, but crashed the Linux kernel for some obscure reason16:06
larscwpwrak: or non-deterministic reconfiguration16:07
lekernelfortunately, the bug was somehow related to the CPU cache, so one day someone tried to run Linux with the caches disabled and it worked ...16:07
lekernelon spartan6, with the exact same verilog code, Linux works with the caches... and I think they have fixed it for virtex4 now as well16:08
wpwraknice. these are all good bugs, ideal for engineers working for stable companies and interested in long-term job security :)16:08
wpwrak(annual progress report: MTBF is up 50% from last year. still many bugs to work around.)16:09
larscat somepoint your workarounds create more bugs than they fix16:10
wpwrakyeah, that's when you should find an excuse to go to a different project :)16:13
larscI think that's why Xilinx is pushing vivado ;)16:22
wpwrakyou mean they lost control of their code ? nice ;)16:23
larscnobody's brave enough to work on the ISE codebase16:24
wpwrakor maybe it already ate all the programmers who got too close16:25
davidc__lekernel: if migen was BSD, I could use it for work; and therefore do bugfixes/feature stuff on work time [with the intent of getting it upstream, ofc]17:00
davidc__lekernel: [well, BSD, or L?GPL with generated-verilog-output-is-not-considered-derived exception]17:01
lekerneldavidc__, cool, thanks for the feedback. what do you work on?17:40
davidc__lekernel: Embedded network security stuff. Can't give too much detail, sorry :(17:52
davidc__lekernel: but all FPGA deployed stuff17:52
Action: wpwrak hates those GMP, MPFR, and MPC dependencies of gcc18:00
azonenberglekernel: I personally don't have a use case for migen since i already have a tool that does what i need18:07
azonenbergthat said, i am in favor of BSDing everything in general18:07
wpwrakhmm, "checking for shl_load... configure: error: Link tests are not allowed after GCC_NO_EXECUTABLES."18:12
wpwraklet's see what google know about that ..18:12
wpwrakah, that's where the libstdc removal comes from :)18:13
lekernelyou can also disable c++ entirely - no software in milkymist-ng requires it18:16
wpwraka wise decision ;-)18:19
wpwrak"milkymist-ng/verilog/lm32/submodule/rtl/lm32_cpu.v does not exist"18:27
wpwrakall there is is verilog/lm32/lm32_config.v18:28
wpwraknothing "lm32" in migen/mibuild either18:28
_florent_lm32 is now a submodule18:32
_florent_http://github.com/milkymist/lm3218:33
wpwrakah, thanks !18:33
lekernelGit law #3: Every positive initial feeling toward submodules has an equal and opposite second feeling. ;)18:33
wpwrakso i check it out and move lm32/* into verilog/lm32/submodule/ ?18:35
lekernelwpwrak, http://stackoverflow.com/questions/3796927/how-to-git-clone-including-submodules18:36
Action: wpwrak deletes milkymist-ng18:37
wpwrakyeah, seems to work18:37
lekernelazonenberg, yes, I know you love NIH :)21:51
lekernelhow is your DDR2 controller coming along?21:51
azonenberglekernel: on hold, i'm swamped with homework this week21:51
GitHub158[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/Kh5mTw21:57
GitHub158migen/master ceb0a99 Sebastien Bourdeauducq: Change license to 2-clause BSD21:57
davidc__whoo; now to evangelize a few people.....22:06
--- Tue Apr 16 201300:00

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