#milkymist IRC log for Thursday, 2013-04-11

larscIf there was crosstalk inside the fpga that would be really bad07:15
larscthe edges on the scl signal are quite spikey, depending on the hysteresis of the pin the logic might pick up a extra clock cycle07:25
larscI think it wouldn't hurt to do some extra hysteresis in the digital domain07:27
wpwraklarsc: well, it could be a synthesis problem or some odd artefact migen introduces. so not "real" crosstalk09:08
wpwraklarsc: and yes, a bit of filtering may be appropriate, considering that we have signal timings that differ by no less than three orders of magnitude09:09
wpwrakan EMI filter that cuts off at, say, 1 MHz would be nice :)09:10
lekernelwpwrak, hahaha, you can examine the generated verilog then :)09:11
lekernelmigen doesn't do anything weird with the fpga (yet)09:12
wpwraklekernel: so the finding this far don't contain anything new/unexpected for you ?09:14
lekernelno, I had already observed the missing ack with the saelae09:15
lekernelthe only new finding so far is that the level converter appears to work correctly with good signal integrity09:15
wpwrak(examine verilog) one of the problems with code generators. it wouldn't exactly be the first one that hides errors in very creative new ways ;-)09:15
wpwrakokay, good. i'll give the signals another look with a scope with a higher sample rate and a better probe setup (right now, the loops are very long, severely limiting the visible frequencies). see if something turns up.09:17
larscwpwrak: something like http://pastebin.com/7yDEZE9v should probably be enough to filter out spikes09:18
wpwrakwhat do you think of outputting the state ?09:18
lekernelsounds like a reasonable next step09:18
_florent_don't know it can help, but I you want to see what is going on in the FPGA, I can integrate miscope in your design.09:18
wpwrakoh, "eq" is an assigment. now a few things are clearer :)09:18
larscwpwrak: yea, we had that discussion before. I voted for assign09:19
lekernelwe should get python to use ordered dictionaries at all times, then we can abuse keyword arguments and use =09:20
wpwrak_florent_: what i want to try is to look at the analog domain and the digital state with my MSO. that way, i don't need to guess from the digital results what exactly is happening in the analog domain at that moment09:20
lekernelin addition to not having to waste time with non-determinism anymore, ever09:20
wpwraklekernel: yeah, a more python-like syntax would be nice09:21
wpwrak(no non-determinism ever again) famous last words ;-)09:21
_florent_wpwrak: ok09:22
wpwrakwow. ISE download completed. i almost didn't believe anymore i'd live to see this :)09:24
wpwrak"tar: Unexpected EOF in archive" ?!?09:28
wpwrakindeed. "only" 5 GB09:28
wpwraklet's try the multi-file download instead ...09:30
larscyou can continue the download with wget -c09:31
wpwrakXilinx, the bloatware company ...09:31
wpwrakdoes that work with their site ?09:31
larscyes, at least it did in the past09:32
larscyou don't even need to fill out the form and everything if you already have the link09:33
wpwrakdidn't work :-( but let's switch to wget anyway09:35
wpwrakit's funny that most web browsers make it really hard to get links to the true locations of things09:38
wpwraknow .. let's undust the other scope. lower bandwidth, better sample rate09:39
wpwrakhmm, do xilinx specify a minimum input slew rate for these IOs ? I see 4 V/us for rising edges. UG381 talks a lot about output slew but not input. oh, and there's even an "I2C" I/O standard :)10:03
wpwraklekernel: btw, while your tutorial seems to suggest that mibuild would have a setup.py, there is none10:38
wpwrakhmm, so ".comb +=" is basically a post-it note for the .eq in the right-hand side to be combinatorial ?10:47
wpwrakwhat's the default for .eq ? combinatorial, synchronized, or something else ?10:48
lekernelno default - it's just an assignment, then you say when it should happen by using the corresponding special property of the Module object10:51
lekerneland yes 'comb' makes it combinatorial10:52
wpwrakah "default" (tmp = x.eq(...)) gives you the reference, but doesn't add it to the design. i see.10:53
wpwrakno way to make "=" do an implicit .rd() if the right-hand side is a signal ? (i suppose the "s" in "v_led = s.rd(led)" is already contained in "led")11:00
lekernelfor simulation? when you have a lot of signals you can use a proxy11:02
lekernelwhich does that11:02
wpwrakwhat's a proxy ? :)11:02
lekernelProxy(simulator, some_object)11:02
lekernelsorry, some_object_p = Proxy(simulator, some_object)11:03
lekerneland then some_object_p.signal === s.rd(some_object.signal)11:03
lekernelworks also for writes11:05
wpwrakmy parser just exploded :) but yes, i see the difficulty if choosing the "right" action, given that all you know about v_led comes from its current value, which is probably not the most reliable thing to use11:06
wpwraki.e., python would have no good way to know that the assignment is   (int) var <- (Signal) expr  which - if it knew - it could convert to  var = design_of(expr).rd(expr)11:07
lekernelbut it does for object properties, so the Proxy solution works fine - and uses wr/rd automatically11:08
wpwrakit's an interesting situation: python gives you enough flexibility to implement what you want in a domain-specific language (superset), but not enough to do it with a nice syntax11:08
lekernelit's also reentrant, since you store the simulator reference only in the Proxy object11:09
lekernelwhat's wrong with the Proxy syntax? you need just one extra line to create the Proxy, then it's transparent11:11
lekerneland you need to specify the simulator reference somehow anyway11:12
wpwrakit's those little extra things. they're not very intuitive.11:13
wpwrakah, so the simulation is "s", not "self" ?11:14
larscpython kind of mixes whether = is assignment or binding, if it is assignment it works, if it is a binding it does not11:14
wpwrakwhat is Blinker then ?11:14
lekernels is the interface to the simulator11:14
lekernelself is the module11:15
wpwrakso "s" represents the simulation state ?11:16
lekernelyesyou can, theoretically, have several simulators running of the same design, and they would not interfere with each other)11:16
wpwrakheh :)11:16
lekernelyes. you can, theoretically, have several simulators running of the same design, and they would not interfere with each other. that's probably not a very useful feature, but it helps to understand how it's done - all the state of a given simulation is stored in s11:16
wpwrakah yes, i see. Blinker comes from before. it's the design.11:16
wpwraki think that's again a case where you have a somewhat artificial separation. the most intuitive way to think of it would be to see Blinker as a class and the simulation as an instantiation. not sure how you'd deal with multiple Blinkers in the same design, though.11:20
lekernelmaybe, but it worked fine like that so far11:20
lekernelfeel free to propose something else11:20
lekernelas you can see I'm often improving the API (aka breaking compatibility)11:21
wpwraka syntax converter :)11:21
wpwrakyes, i guess that happens when you find out about some python trick that allows you to go a little deeper into what the interpreter does behind the scene11:22
wpwraknothing suspicious to see also with the other scope (besides the slew rate, which may or may not be a problem, depending on how trigger-happy the IOs are). i hope i'll find some answers in the digital domain :)11:59
wpwrakah, does migen happen have a UART that could be used for diagnostics (via the debug board) ?12:00
larscmilkymist-ng has one12:02
larscand I think _florent_'s miscope also uses it12:02
playthatbeatstrange, my milkymist now displays the patch title during a performance if i hit F1 to choose vid input 114:12
playthatbeatit never used to do this??!! wtf?14:13
Fallenouwhat does F1 do?14:15
Fallenou(or is supposed to do)14:15
playthatbeatit should select the composite input 114:22
playthatbeatit still DOES select input 114:22
playthatbeatvideo in 114:22
playthatbeatbut also throws on the title of th epatch as an overlay?14:22
playthatbeatf2 and f3 select inputs 2 and 3 and are fine14:23
playthatbeatno title appears14:23
playthatbeatthis only started today, didn't do it last week14:23
playthatbeatno matter, i just stick to inputs 2 and 3 for now, have to work..14:24
lekernelhi bhamilton16:58
GitHub68[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/2zUkjQ16:59
GitHub68migen/master 75d33a0 Sebastien Bourdeauducq: fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)16:59
wpwrakmibuild/README: the 6 lines intro fails with "NameError: name 'counter' is not defined". if i add  counter = Signal(2)  (does that make sense ?) i get a bit further18:34
wpwrakah no, needs more bits18:34
wpwrakis xilinx wanted to be more customer-hostile, they'd have to start mailing anthrax letters ...18:43
wpwrakphew. seems i made it through license hell. until the next breakage ...18:47
davidc__wpwrak: don't give them ideas.18:48
wpwrakit's very nice that mibuild takes care of the whole environment setup (or should i say "upset" ?) for the xilinx tools. that avoids all the library conflicts with the rest of the system.22:31
--- Fri Apr 12 201300:00

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