| larsc | If there was crosstalk inside the fpga that would be really bad | 07:15 |
|---|---|---|
| larsc | the edges on the scl signal are quite spikey, depending on the hysteresis of the pin the logic might pick up a extra clock cycle | 07:25 |
| larsc | I think it wouldn't hurt to do some extra hysteresis in the digital domain | 07:27 |
| wpwrak | larsc: well, it could be a synthesis problem or some odd artefact migen introduces. so not "real" crosstalk | 09:08 |
| wpwrak | larsc: and yes, a bit of filtering may be appropriate, considering that we have signal timings that differ by no less than three orders of magnitude | 09:09 |
| wpwrak | an EMI filter that cuts off at, say, 1 MHz would be nice :) | 09:10 |
| lekernel | wpwrak, hahaha, you can examine the generated verilog then :) | 09:11 |
| lekernel | migen doesn't do anything weird with the fpga (yet) | 09:12 |
| lekernel | build/top.v | 09:12 |
| wpwrak | lekernel: so the finding this far don't contain anything new/unexpected for you ? | 09:14 |
| wpwrak | findingS | 09:14 |
| lekernel | no, I had already observed the missing ack with the saelae | 09:15 |
| lekernel | the only new finding so far is that the level converter appears to work correctly with good signal integrity | 09:15 |
| wpwrak | (examine verilog) one of the problems with code generators. it wouldn't exactly be the first one that hides errors in very creative new ways ;-) | 09:15 |
| wpwrak | okay, good. i'll give the signals another look with a scope with a higher sample rate and a better probe setup (right now, the loops are very long, severely limiting the visible frequencies). see if something turns up. | 09:17 |
| larsc | wpwrak: something like http://pastebin.com/7yDEZE9v should probably be enough to filter out spikes | 09:18 |
| wpwrak | what do you think of outputting the state ? | 09:18 |
| lekernel | sounds like a reasonable next step | 09:18 |
| _florent_ | hi | 09:18 |
| _florent_ | don't know it can help, but I you want to see what is going on in the FPGA, I can integrate miscope in your design. | 09:18 |
| wpwrak | oh, "eq" is an assigment. now a few things are clearer :) | 09:18 |
| _florent_ | *If | 09:19 |
| larsc | wpwrak: yea, we had that discussion before. I voted for assign | 09:19 |
| lekernel | we should get python to use ordered dictionaries at all times, then we can abuse keyword arguments and use = | 09:20 |
| wpwrak | _florent_: what i want to try is to look at the analog domain and the digital state with my MSO. that way, i don't need to guess from the digital results what exactly is happening in the analog domain at that moment | 09:20 |
| lekernel | in addition to not having to waste time with non-determinism anymore, ever | 09:20 |
| wpwrak | lekernel: yeah, a more python-like syntax would be nice | 09:21 |
| wpwrak | (no non-determinism ever again) famous last words ;-) | 09:21 |
| _florent_ | wpwrak: ok | 09:22 |
| wpwrak | wow. ISE download completed. i almost didn't believe anymore i'd live to see this :) | 09:24 |
| wpwrak | "tar: Unexpected EOF in archive" ?!? | 09:28 |
| wpwrak | indeed. "only" 5 GB | 09:28 |
| wpwrak | let's try the multi-file download instead ... | 09:30 |
| larsc | you can continue the download with wget -c | 09:31 |
| wpwrak | Xilinx, the bloatware company ... | 09:31 |
| wpwrak | does that work with their site ? | 09:31 |
| larsc | yes, at least it did in the past | 09:32 |
| larsc | you don't even need to fill out the form and everything if you already have the link | 09:33 |
| wpwrak | didn't work :-( but let's switch to wget anyway | 09:35 |
| wpwrak | it's funny that most web browsers make it really hard to get links to the true locations of things | 09:38 |
| wpwrak | now .. let's undust the other scope. lower bandwidth, better sample rate | 09:39 |
| wpwrak | hmm, do xilinx specify a minimum input slew rate for these IOs ? I see 4 V/us for rising edges. UG381 talks a lot about output slew but not input. oh, and there's even an "I2C" I/O standard :) | 10:03 |
| wpwrak | lekernel: btw, while your tutorial seems to suggest that mibuild would have a setup.py, there is none | 10:38 |
| wpwrak | hmm, so ".comb +=" is basically a post-it note for the .eq in the right-hand side to be combinatorial ? | 10:47 |
| wpwrak | what's the default for .eq ? combinatorial, synchronized, or something else ? | 10:48 |
| lekernel | no default - it's just an assignment, then you say when it should happen by using the corresponding special property of the Module object | 10:51 |
| lekernel | and yes 'comb' makes it combinatorial | 10:52 |
| wpwrak | ah "default" (tmp = x.eq(...)) gives you the reference, but doesn't add it to the design. i see. | 10:53 |
| lekernel | yes | 10:55 |
| wpwrak | no way to make "=" do an implicit .rd() if the right-hand side is a signal ? (i suppose the "s" in "v_led = s.rd(led)" is already contained in "led") | 11:00 |
| lekernel | for simulation? when you have a lot of signals you can use a proxy | 11:02 |
| lekernel | which does that | 11:02 |
| wpwrak | what's a proxy ? :) | 11:02 |
| lekernel | Proxy(simulator, some_object) | 11:02 |
| lekernel | sorry, some_object_p = Proxy(simulator, some_object) | 11:03 |
| lekernel | and then some_object_p.signal === s.rd(some_object.signal) | 11:03 |
| lekernel | works also for writes | 11:05 |
| wpwrak | my parser just exploded :) but yes, i see the difficulty if choosing the "right" action, given that all you know about v_led comes from its current value, which is probably not the most reliable thing to use | 11:06 |
| wpwrak | i.e., python would have no good way to know that the assignment is (int) var <- (Signal) expr which - if it knew - it could convert to var = design_of(expr).rd(expr) | 11:07 |
| lekernel | but it does for object properties, so the Proxy solution works fine - and uses wr/rd automatically | 11:08 |
| wpwrak | it's an interesting situation: python gives you enough flexibility to implement what you want in a domain-specific language (superset), but not enough to do it with a nice syntax | 11:08 |
| lekernel | it's also reentrant, since you store the simulator reference only in the Proxy object | 11:09 |
| lekernel | what's wrong with the Proxy syntax? you need just one extra line to create the Proxy, then it's transparent | 11:11 |
| lekernel | and you need to specify the simulator reference somehow anyway | 11:12 |
| wpwrak | it's those little extra things. they're not very intuitive. | 11:13 |
| wpwrak | ah, so the simulation is "s", not "self" ? | 11:14 |
| larsc | python kind of mixes whether = is assignment or binding, if it is assignment it works, if it is a binding it does not | 11:14 |
| wpwrak | what is Blinker then ? | 11:14 |
| lekernel | s is the interface to the simulator | 11:14 |
| lekernel | self is the module | 11:15 |
| wpwrak | so "s" represents the simulation state ? | 11:16 |
| lekernel | yesyou can, theoretically, have several simulators running of the same design, and they would not interfere with each other) | 11:16 |
| lekernel | oops | 11:16 |
| wpwrak | heh :) | 11:16 |
| lekernel | yes. you can, theoretically, have several simulators running of the same design, and they would not interfere with each other. that's probably not a very useful feature, but it helps to understand how it's done - all the state of a given simulation is stored in s | 11:16 |
| wpwrak | ah yes, i see. Blinker comes from before. it's the design. | 11:16 |
| wpwrak | i think that's again a case where you have a somewhat artificial separation. the most intuitive way to think of it would be to see Blinker as a class and the simulation as an instantiation. not sure how you'd deal with multiple Blinkers in the same design, though. | 11:20 |
| lekernel | maybe, but it worked fine like that so far | 11:20 |
| lekernel | feel free to propose something else | 11:20 |
| lekernel | as you can see I'm often improving the API (aka breaking compatibility) | 11:21 |
| wpwrak | a syntax converter :) | 11:21 |
| wpwrak | yes, i guess that happens when you find out about some python trick that allows you to go a little deeper into what the interpreter does behind the scene | 11:22 |
| wpwrak | nothing suspicious to see also with the other scope (besides the slew rate, which may or may not be a problem, depending on how trigger-happy the IOs are). i hope i'll find some answers in the digital domain :) | 11:59 |
| wpwrak | ah, does migen happen have a UART that could be used for diagnostics (via the debug board) ? | 12:00 |
| larsc | milkymist-ng has one | 12:02 |
| larsc | and I think _florent_'s miscope also uses it | 12:02 |
| playthatbeat | strange, my milkymist now displays the patch title during a performance if i hit F1 to choose vid input 1 | 14:12 |
| playthatbeat | it never used to do this??!! wtf? | 14:13 |
| Fallenou | what does F1 do? | 14:15 |
| Fallenou | (or is supposed to do) | 14:15 |
| playthatbeat | it should select the composite input 1 | 14:22 |
| playthatbeat | it still DOES select input 1 | 14:22 |
| playthatbeat | video in 1 | 14:22 |
| playthatbeat | but also throws on the title of th epatch as an overlay? | 14:22 |
| playthatbeat | f2 and f3 select inputs 2 and 3 and are fine | 14:23 |
| playthatbeat | no title appears | 14:23 |
| playthatbeat | this only started today, didn't do it last week | 14:23 |
| playthatbeat | no matter, i just stick to inputs 2 and 3 for now, have to work.. | 14:24 |
| lekernel | hi bhamilton | 16:58 |
| GitHub68 | [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/2zUkjQ | 16:59 |
| GitHub68 | migen/master 75d33a0 Sebastien Bourdeauducq: fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec) | 16:59 |
| wpwrak | mibuild/README: the 6 lines intro fails with "NameError: name 'counter' is not defined". if i add counter = Signal(2) (does that make sense ?) i get a bit further | 18:34 |
| wpwrak | ah no, needs more bits | 18:34 |
| wpwrak | is xilinx wanted to be more customer-hostile, they'd have to start mailing anthrax letters ... | 18:43 |
| wpwrak | phew. seems i made it through license hell. until the next breakage ... | 18:47 |
| davidc__ | wpwrak: don't give them ideas. | 18:48 |
| wpwrak | ;-) | 18:48 |
| wpwrak | it's very nice that mibuild takes care of the whole environment setup (or should i say "upset" ?) for the xilinx tools. that avoids all the library conflicts with the rest of the system. | 22:31 |
| --- Fri Apr 12 2013 | 00:00 | |
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