#milkymist IRC log for Wednesday, 2013-04-10

wpwrakthings are looking good. something is coming, and it's from the local postal distribution center, merely some 10 blocks away. i hope it's the parcel, not just a note.12:17
wpwraksb0: shipment received ! with no customs hassles at all that's how i like it :)15:43
sb0so now be careful: no 5V15:43
wpwrakwho uses 5 V ? ;-)15:44
sb0I actually cut the 5V pins of my M1 so that I can't inadvertently plug the HDMI board into them15:44
sb0also used cardboard and double-sided tape on VGA/audio connectors to hold it in place during HDMI connections/disconnections15:45
wpwrak(cut 5 V) nice :)15:48
wpwraklemme see how it fits ..15:48
sb0the 5V pins are those closest to the VGA/audio side15:48
sb0they should match the two unsoldered pads on the HDMI board15:49
wpwraklooks good. lemme check the schematics, just to be sure15:52
wpwrakit's actually kinda funny that the board says "Not 5V tolerant" right next to the connector that provides 5 V15:54
wpwrakokay. all looks well regarding 5 V15:56
wpwrakthe HDMI connectors face towards LED/buttons/USB15:57
wpwrakperfect. where do you keep the schematics, gerbers, etc. of the mider board ?15:57
sb0I'll send you an updated http://lists.milkymist.org/pipermail/devel-milkymist.org/attachments/20130313/a4ba7f8f/attachment.py16:01
wpwraki'll also need to install migen and the rest of the development environment16:03
sb0python3 + mibuild + migen + ISE16:04
sb0and milkymist-ng16:04
wpwrakany preferred version of ISE ?16:05
sb0if you have one that worked for the old soc, it should still be fine16:06
sb0otherwise take the latest16:06
wpwraklost the old environment in one of those disk failures, so it'll all be fresh16:07
wpwrakokay, layout is clear. ah, do you already decode HDMI and produce an image (on VGA) ?16:13
sb0no, the series of bugs irritated me beyond reasonable levels so I did something else for a while16:14
sb0will get back to it in a short while...16:15
wpwrakso there are more bugs ? :)16:15
sb0I didn't touch the data interface since last time...16:15
sb0next step is to throw the raw data into the DRAM and see if I get something else than garbage16:16
sb0almost everything has semi-random behaviour ...16:16
wpwrakkewl. if all else fails, you can sell it to the military as a high-entropy random number generator ;-)16:17
wpwrakafter all, if it's only sometimes random, that makes it more random, right ? :)16:18
wpwrakISE download, first stage, 2 hours left :-(16:51
larscwe couldn't get it to work so far17:36
larscI think they just break more and more things on purpose so everybody switches to vivado17:36
sb0only tried 14.4 ...17:39
wpwrakvivado is non-free ? i actually ended up beginning to download vivado. it somehow appeared en route to webpack.17:39
sb0larsc, what's broken?17:40
wpwrakokay, let's switch to 14.4 then. new download, new luck17:40
sb0vivado is free of charge, but when I tried it it was ludicrously slow17:40
sb0'ludicrously' as in '15min compilation for a LED blinker'17:40
larscsb0: I only heard my college cursing, I think it was aborting with some obscure error when building the bistream17:41
wpwraklarsc: your colleagues in germany ?17:42
larscwell there is only one17:42
larscor did you mean colleague's17:43
wpwrakah. Mr. Macleod then :)17:43
wpwrakhmm, he's been with you to romania then. so i can't make the joke that you heard the curses across hundreds of kilometers17:43
larscah, the highlander17:44
wpwrak"There can be only one" :)17:44
lekernelwpwrak, emailed you the EDID tester source + a bitstream18:25
lekernel(compatible with the new migen api)18:25
lekernelit also blinks a LED on the pixel clock, you should be able to control the frequency with xrandr18:26
lekernelthe HDMI port is the one close to VGA/audio (left side when facing the connectors)18:27
wpwrakthanks ! setting up the test PC ...18:29
wpwrakah, ubuntu is not happy with my streamlined system. well, that's not entirely unexpected. plan B then ...18:37
sb0tried archlinux?18:40
wpwraknaw, it didn't come to that yet :)18:42
Hawk777Anyone else get a page not found just going to xilinx.com, hovering Products, and clicking Development Tools?18:59
Hawk777Or for that matter just clicking Products?18:59
sb0yes, same here19:01
sb0seems wpwrak started his download just in time :)19:02
wpwrakwhee, the autocrap family has a new member: autopoint19:09
wpwrakthe download still seems to be going well. except that it slowed down. now it's "7 hours left" :-(19:15
GitHub152[migen] sbourdeauducq pushed 3 new commits to master: http://git.io/HZ_YTQ19:18
GitHub152migen/master 692794a Sebastien Bourdeauducq: flow: use Module and new Record APIs19:18
GitHub152migen/master df1ed32 Sebastien Bourdeauducq: genlib/record/connect: add match_by_position19:18
GitHub152migen/master 6ce8562 Sebastien Bourdeauducq: flow: match record fields by position19:18
wpwrakto load top.bit ... pld load top.bit  and then is it ready or do i need to do something else ?19:19
GitHub46[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/92lMug19:19
GitHub46milkymist-ng/master 950d3a4 Sebastien Bourdeauducq: framebuffer: use new flow API19:19
sb0then it's ready... plug the HDMI cable and it should show in xrandr19:19
wpwrakdrums ...19:20
sb0note that there might be problems if you plug it before the bitstream is loaded - the HPD pin is held permanently asserted due to lack of IO pins19:20
sb0it didn't cause major issues on my two nvidia cards - it keeps retrying EDID reads, but does not give up19:20
wpwrakxrandr sees it19:21
sb0ok. now set a mode and the LED should be blinking, and I2C not working anymore.19:22
wpwraklet's see ...19:22
sb0looks good19:22
wpwrakLED blinks happily19:23
wpwrakafter xrandr --output DVI-1 --mode 640x48019:24
sb0is xrandr --verbose capable of displaying the EDID?19:24
sb0with the bug that would fail19:24
wpwrak"DVI-1 disconnected" suggests that it may not ...19:24
sb0ok. so you can reproduce it.19:24
wpwrakan no, no EDID in sight. only one from the other screen19:25
wpwrakthat much about "it only happens in the northern hemisphere" :)19:26
wpwrakone signal looks pretty good on the M1 side, with bursts of ~4 x 10 cycles every few seconds. 4 Vpp, says my scope. to be verified. the other sits at 2 V, apparently without activity.19:37
wpwraklemme verify that i got the right ones ...19:38
sb0should be 3.3V ...19:40
sb0I got both SCL and SDA nicely with the saelae19:40
wpwrakscope thinks it's 4 V. will check with a voltmeter in a moment. the HDMI connectors are good grounds, right ?19:41
sb0no, they aren't19:42
sb0the shells are connected to ground with a parallel RC circuit19:43
wpwrakah, i see. let's see what else i can use that's not too fragile ...19:45
wpwrakUSB looks good :)19:46
sb0soldering a row of 3 pins on top of the connector that goes to M1 works nicely19:46
sb0USB is also not a good ground19:47
wpwrakah, damn. the shield is RC'ed too19:48
wpwrakah, and the "4 V" was actually ~3.3 V. so far, so good.19:55
wpwraknow let's see what's up with the other signal19:55
wpwrakthat was the wrong pin. makes sense then, too. now i see a nice and clean signal on the M1 side19:55
wpwrakxrandr still thinks it's disconnected19:57
wpwrakthis is what the M1 side looks like: http://downloads.qi-hardware.com/people/werner/ming/edid/mix-scl-sda-m1-10us.png20:07
wpwrakand here's the entire data block: http://downloads.qi-hardware.com/people/werner/ming/edid/mix-scl-sda-m1-200us.png20:09
GitHub103[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/4xeOOg20:15
GitHub103migen/master 1cc4c8e Sebastien Bourdeauducq: uio: remove Trampoline (Python 3.3 provides generator delegation instead)20:15
GitHub103migen/master 746acda Sebastien Bourdeauducq: ioo: move to genlib20:15
wpwrakif i reload the bitstream, there's a rather extensive dialog, with signals that look just as nice20:19
larscdoes it look any different with and without hdmi on?20:25
wpwrakhow would the two states differ ?20:27
larscthe amount noise supposedly20:28
wpwrakno, i mean: what would i change in the system to be "without hdmi on" ?20:30
wpwraki think before the xrandr --mode, no video signal is output, if you mean that20:31
sb0xrandr --output xxx --off20:31
sb0I think so20:31
wpwraklet's try --off and a reconfiguration20:31
wpwrakoh, now it came back. just with the --off20:33
wpwrakbefore, i once tried and it stayed "disconnected"20:33
wpwrakyeah, --off seems to work20:33
wpwrakeven without touching the fpga20:34
sb0same here20:38
wpwrakthe signals also look clean on the other side of the level converters20:41
wpwraknot quite as lovely, but should be sufficiently good20:41
wpwraklet's see what's happening with the pixel data20:44
wpwrakthe video side looks pretty dead20:50
wpwraki wonder if it could simply be an I2C/DDC request the M1 doesn't understand20:51
larscit's all the same20:57
larscor at least should be20:57
larsci2c read on address 0x5020:57
sb0I remember seeing the M1 failing to ack the 0x50 address when the video is on20:59
wpwrakhere's a numeric dump at 100 ns/Sa, suitable for viewing with gnuplot: http://downloads.qi-hardware.com/people/werner/ming/edid/unanswered-scl-sda-100ns.gp.bz221:19
wpwrakto visualize, plot "foo.gp" using 1:($2+4.5) with lines, "foo.gp" using 1:3 with lines21:19
wpwraknow, let's decode it ...21:19
larsca couple of reads for 0x50 without an ack21:23
GitHub109[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/y4Mzqg21:27
GitHub109migen/master 4c9018e Sebastien Bourdeauducq: fhdl/visit: add TransformModule21:27
GitHub109migen/master 72ef4b9 Sebastien Bourdeauducq: ioo+pytholite: use new Module API21:27
wpwrakmy decoder says S50WN. i think that means it agrees :)21:36
wpwrakactually no. it's a write, according to my decoder.21:38
larscuhm yes21:39
larscit might want to read a certain subpage21:40
wpwraknow, as i know sebastien, he probably didn't implement writes ... :) let's see ...21:40
larscit looks it if it ignores the read/write bit21:43
larscbut always responds21:44
wpwrakmilkymist-ng/milkymist/dvisampler/edid.py:179 does indeed look a little suspicious21:44
wpwraki seems to consider the bit, but doesn't know what to do with a write21:44
larschm, am I missing something or is the WAIT_START state not implemented?21:49
wpwrakand 0x50 is indeed the EDID21:50
wpwrakyeah, looks like it21:52
wpwrakor maybe there's some default or such. can't quite make sense of it yet21:52
larscmight be the for state in states at the bottom21:53
wpwrakanyway, i think we have an explanation :)21:53
wpwrakyeah, that could be some default clause. or maybe not ;)21:53
larscactually the code looks as if it should handle writes propertly21:54
larscbut I think it is possible that it never leaves the READ, ACK_READ cycle21:57
wpwrakisn't WAIT_START the wait for a start bit ?21:57
wpwrakfor a write, it would still have to receive the value21:57
larscit does21:58
wpwrakah yes, line 13421:59
larscbut a stop condition should reset the fsm22:00
larscand there does not seem to be stop support22:00
larscstop = Signal()22:02
larscself.comb += stop.eq(scl_i & sda_rising)22:02
larscand then If(stop, fsm.next_state(fsm.WAIT_START)).Else(... for each state22:03
wpwrakbut doesn't a start the FSM as well ?22:05
larscah, ok22:07
larscthats why it adds it to each state22:07
wpwrakit should output the state on some unused pins. then it would be easy to monitor what's going on.22:12
wpwrakhmm, since sebastien isn't around, i'll just post a summary of what we have so far on the list. maybe it already rings a bell.22:24
larschm, if I simulate things, start is set whenever sda is falling, even if scl is low22:53
wpwrakhmm. i think i should be able to see the pixel clock. let's look for it again ...22:54
larscah, that was the 20 cycle delay line22:54
wpwrakmaybe it's the clock input cross-talking somewhere in the logic. the clock is very fast in comparison, 30+ MHz vs. ~40 kHz I2C clock23:14
wpwrak31.502 MHz, to be exact23:25
--- Thu Apr 11 201300:00

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