#milkymist IRC log for Thursday, 2013-03-28

sh4rm4"Prices for ABAX chips range from $105 to $200 in 1,000 unit quantities." http://www.bdti.com/InsideDSP/2010/03/18/Tabula02:09
lekernelsh4rm4, hum, that's a 2010 article. they weren't shipping by then.10:28
lekernelbut this looks surprisingly cheap10:29
lekernelhehe, running at 1024*768 32bpp with only 256 pixels buffered on-chip17:09
lekernelthe old soc required thousands for doing the same at 16bpp17:09
lekernelI'm sure we can do 1080p if the 140MHz DAC accepts being overclocked to 148.517:10
lekernellet me try tha17:10
lekernelt17:10
lekernelyeh, the old soc has 1024 pixels buffered for coping with half the bandwidth milkymist-ng does with a 256-deep buffer17:13
wpwrakthe buffering is for the burstiness of the transfer from RAM ?17:22
lekernelyes17:23
lekerneland when DRAM has to deal with other requests (CPU etc.)17:23
lekernelmilkymist-ng lets you queue several commands into the DRAM controller with dedicated slots (not just one and with arbitration like the old SoC), so it handles better the loads17:26
lekernelit reorders the pending requests to improve page hit rate and reduce read/write turnaround, too17:27
wpwrakso you're now in the < 7 us delay range17:27
lekerneland DRAM is run at 2x the system clock rate17:27
wpwrakah no, < 2 us even17:28
lekernelthe controller can issue both a precharge/activate and a read/write command to another bank in the same cycle17:28
lekernel(system cycle)17:28
wpwrakso this is not only higher bandwidth for linear transfers but also faster switching between banks ?17:29
lekernelso you can have up to 133 million DRAM commands per second on a slowtan6 that can only meet system timing at 83MHz17:29
lekernelyes17:29
lekernellater I'll want to do the same thing with a more serious FPGA and DDR3-1600 or so. it's just multiplying numbers, keeping the same arch.17:30
wpwrakhow is stability ? have you done any long-running torture-testing yet ?17:31
lekernelnot as much testing as the old controller... actually I want to at least try 1080p as a test before sending the bug-ridden HDMI data to DRAM17:32
lekernelI wrote a traffic generator for the old controller and tested it with dozens of terabytes of data, but I have not ported it17:33
wpwrakyeah, the old one was good. i think it never gave us any trouble. so your methodology appears to work :)17:40
GitHub63[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/9u706Q18:08
GitHub63milkymist-ng/master 8fd092c Sebastien Bourdeauducq: crg: support VGA pixel clock reprogramming18:08
GitHub69[misp] sbourdeauducq pushed 1 new commit to master: http://git.io/x3U-gw18:09
GitHub69misp/master 9a7c3d9 Sebastien Bourdeauducq: agg_test: 1024x768 demo18:09
GitHub150[milkymist-ng] sbourdeauducq pushed 3 new commits to master: http://git.io/a97djA19:47
GitHub150milkymist-ng/master b603eaf Sebastien Bourdeauducq: m1crg: allow up to 150MHz pixel clock19:47
GitHub150milkymist-ng/master 4dcec32 Sebastien Bourdeauducq: top: allocate one more ASMI port to framebuffer19:47
GitHub150milkymist-ng/master 854c046 Sebastien Bourdeauducq: framebuffer: process two pixels per system clock cycle19:47
lekernelgrmbl 148.25Mhz pixel clock19:50
lekernel= 50*593/20019:50
lekernelwhat a mess19:50
lekernellet's hope 148 works19:51
larscshould work19:51
lekernelyay, it works!20:43
Fallenouso you got 1080p framebuffer ? :)20:59
--- Fri Mar 29 201300:00

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