#milkymist IRC log for Thursday, 2013-03-21

GitHub195[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/UkGYtg09:41
GitHub195migen/master a94bf3b Sebastien Bourdeauducq: genlib/cdc/MultiReg: output clock domain defaults to sys09:41
lekernelmeh11:00
lekernelI cut open a cheap HDMI cable with the intention of shortening one data pair to check that my design would detect and compensate for the added skew11:01
lekernelthere are no pairs lol, just conductors in bulk11:01
lekernelthis shines an interesting light on the earlier DDC problems. high impedance (5k) signals buried among 8 signals switching at hundreds of MHz for 3 meters doesn't sound quite right.11:02
lekernelI wonder if my monitor is capable of dealing with such a cable...11:03
lekernelif so maybe adding some hundred-ish pF capacitor on the DDC signals at the HDMI adapter card would help filtering some of the crosstalk11:03
lekernelaha! I found a I2C EEPROM datasheet that recommends adding such a capacitor (plus a series resistor, even) on SCL for DDC applications11:08
larscor you do the filter in hdl11:10
lekernelwell that windowing + average somehow didn't work... and I won't bother further if a 0.1 cent capacitor solves the problem11:28
lekernelhow are you, by the way?11:28
larscgood11:30
larscleaving the hospital tomorrow11:30
larscand the food here isn't even that bad11:31
Fallenougood to know you're ok !13:09
GitHub8[milkymist-ng] sbourdeauducq pushed 3 new commits to master: http://git.io/bSGZLQ14:34
GitHub8milkymist-ng/master bb566c9 Sebastien Bourdeauducq: software/bios: change boot order14:34
GitHub8milkymist-ng/master a6a3d93 Sebastien Bourdeauducq: software: add videomixer base files14:34
GitHub8milkymist-ng/master 2315544 Sebastien Bourdeauducq: software/videomixer: quick hack for phase detection14:34
lekernelphase detector seems to work... so except perhaps that still not fully explained DDC issue the hdmi extension board should be all ok15:03
Fallenou:)15:05
lekernelhttps://twitter.com/Milkymist_Labs/status/314726353603809280 <= it reports data arrives earlier on the shortened lane15:06
_florent_nice hack!15:11
Fallenouahah15:29
GitHub164[milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/zkzAXQ18:07
GitHub164milkymist-ng/master fa2331e Sebastien Bourdeauducq: dvisampler/clocking: generate pix reset18:07
GitHub164milkymist-ng/master 7c4ca4f Sebastien Bourdeauducq: dvisampler/datacapture: deserialize to 10 bits18:07
lekernelhmm, with TMDS if the last bits received are a control word (eg 1101010100) do I always know I'm at a word boundary? or can I ever get 1101010100 from the concatenation of parts of two other valid symbols?18:23
larscaren't there sync symbols?18:28
larscI think the idea is that you can't get one of the sync characters by accident18:31
larscso it should work18:32
lekernelThe high-transition content of the characters transmitted during the blanking period form the basis for character boundary synchronization at the decoder. While these characters are not individually unique in the serial data stream, they are sufficiently alike that the decoder may uniquely detect the presence of a succession of them during transmitted blanking intervals. The exact algorithm for this detection is an implementation detail18:36
lekernel beyond the scope of this document, but minimum conditions for receiver synchronization are defined.18:36
lekernelwhy make it simple ....18:36
lekerneland then it just says "3.3.2 Data Synchronization The receiver is required to establish synchronization with the data streams during any blanking period greater than 128 characters in length."18:37
lekernelomg the xilinx application note code is again full of "rawdata <=#1 rawword;" and "synthesis parallel_case full_case"18:38
larscit's probably in their coding style guidlines that this is a good idea, wouldn't surprise me18:44
_florent_why not dumping a complete data stream to the ddr and send it to your computer over serial or udp and try to undersand every thing and reconstruct the frame using python for example?19:21
_florent_and use it in your simulation for prototyping19:25
larscthat's half the fun19:29
larsc(but twice as productive) ;)19:29
lekernelonly if I run into bugs19:34
_florent_don't know if if can be useful, but I'm working on the refactoring of miscope19:39
_florent_should be working in a few days19:39
_florent_it can output vcd files19:40
_florent_and use migen if course19:40
lekernelI wonder how hard it would be to use Wolfgang's fpgatools to dynamically reroute signals to the analyzer in no time19:53
lekernelsimilar to what Werner did with xdl, minus the proprietary bloatware19:53
lekernelif there are no glitches, you could even reroute while the fpga is running, using partial reconfiguration19:55
larscjust stumbeed upon this www.latticesemi.com/documents/RD1097.pdf20:45
lekernelyeh but their character synchronizer is a nonportability-optimized hard block20:47
antgreendoes xilinx ship any tool to help visualize they mapping of your design?20:47
lekernelmapping at what level?20:48
antgreenI mean, I want to see how the FPGA is being used at the physical level20:49
lekernelyes, with fpga editor20:49
antgreenbah.. that garbage won't run on my Fedora box20:49
antgreenmissing the right motif libs20:49
lekernelif you don't care about the placement, just what type of resources are being used and how they are connected, you can open the netlist with the less buggy planahead20:49
antgreenI just want a fun picture20:50
lekernelplanahead can show you some of the placement too20:50
lekernelbut not the detailed routing20:50
larscantgreen: I just linked the version of the lib it wants to and newer version, works fine20:50
lekernelit could be enough for a fun picture20:50
antgreenwill try20:51
antgreenwhich file do I open with planahead?20:51
lekernelncd I guess20:51
lekernelbut you need to go all the way through, create a "new project" etc.20:52
lekernelfpga editor doesn't have this bureaucracy, but the UI is still pretty horrid20:52
antgreensymlink created. now it's asking for an older libstdc++.   hopefully there's a compat package20:53
lekernelyeh there is20:54
antgreenyou'd think motif would be gone by now20:54
lekerneland then you need to do export DISPLAY=:020:54
lekerneland make sure the old x11 bitmap fonts are installed20:54
larscI did something similar for wolfgangs fpga lib some time ago http://metafoo.de/Screenshot-FPGA%20Viewer3.png20:55
antgreeny20:55
larscDoesn't show utilisation though yet20:55
antgreenWind/U Error (193): X-Resource: DefaultGUIFontSpec (-*-helvetica-medium-r-normal-*-14-*) does not fully specify a font set for this locale20:56
antgreenbah20:56
lekernelyes, you need to install the old fonts and restart your x server20:57
lekernelxorg-fonts-75dpi + xorg-fonts-100dpi20:58
lekernelseems to work ... :)21:57
GitHub97[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/62TXlg21:57
GitHub97milkymist-ng/master 515cdb2 Sebastien Bourdeauducq: dvisampler: character synchronization21:57
lekernel_florent_, MultiRegImpl should not be used directly, use MultiReg instead22:59
lekernelsince it allows hooks to eg add platform-dependent synthesis directives22:59
lekernelalso it's meant to be a double-latch, not a general purpose shift register ...23:00
--- Fri Mar 22 201300:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!