#milkymist IRC log for Monday, 2013-03-18

_florent_Hi!09:35
_florent_I have some questions / suggestions about Migen09:36
_florent_for some modules, I want to be able to pass all in/out signals directly in parameters09:36
_florent_but I also want to be able to use those modules with only some of the parameters09:37
_florent_and that the others use their default values. (ie reset values)09:37
_florent_for example on this code: http://pastebin.com/Dk1vBmUi09:37
_florent_I'm using an ifthenelse function to declare the signal if it is not passed on parameters09:38
_florent_but I don't find it very elegant...09:38
_florent_lekernel: do you have suggestions to improve that? I was thinking of adding an optionnal parameter to Signal class:09:39
_florent_self.c = ifthenelse(c, c, Signal())09:39
_florent_can become:09:39
_florent_self.c = Signal(from=c) (from is maybe not appropriated).09:40
_florent_if from is not None: self.c = from09:40
_florent_if from is None we created a new signal.09:40
_florent_but I'm not sure you'll find that more elegant ;)09:40
lekernelhow about always declaring signals in the module, eg self.c = Signal()09:40
lekernelinstead of passing them as parameters09:41
lekernelthen you use object_instance.c in other statements?09:41
_florent_because for some case it is interesting to directly pass in in parameter09:41
_florent_for example for the oddr:09:42
_florent_I only need this line09:42
_florent_self.submodules.oddr = oddr.ODDR(c=self.clk, d1=1, d2=0, q=self.hdmi_clk)09:42
_florent_if not passed in parameter I will need to affect each signal manually09:43
lekernelyou can do09:44
lekernelif c is None: c = Signal()09:44
lekernelself.c = c09:44
lekernelor - how about using Instance("ODDR", ...) directly? feels a bit weird to have a ODDR module with just a ODDR instance09:45
_florent_just because I have created some xilinx primitive module09:46
lekernelI'd rather use the Instance directly every time...09:46
lekernelkeep it simple09:46
_florent_hmm... yes but no :)09:47
_florent_this is simple for the oddr09:47
_florent_but for the plle2_base for example09:47
_florent_it's easier to have a class than to use the Instance each time09:48
_florent_in this module:09:48
_florent_http://github.com/Florent-Kermarrec/milkymist-ng-kc705/blob/master/milkymist/kc705crg/__init__.py09:48
_florent_the plle2_base is done in 8 lines09:49
lekernelhow about using a function, instead?09:49
lekernelself.specials += plle2_base(...)09:50
lekerneland plle2_base returns Instance09:50
lekernelthen we can handle None in the Instance IOs09:50
lekerneleg treat it as 0 for inputs and disconnected for outputs09:51
_florent_yes why not, it will be almost the same since in the module I'm only instanciating the verilog09:51
lekernelif you want to pass a different default you can use eg Instance.Input("port", value or 2)09:51
_florent_yes, can be interesting09:52
lekernelI'd like to keep the Modules with IO signals as members...09:53
_florent_In fact I was having an issue with my code:09:53
_florent_when I was using self.submodules.oddr = oddr.ODDR(c=self.clk, d1=1, d2=0, q=self.hdmi_clk)09:53
_florent_I want that ce, s and r use their default values which is not the case.09:53
_florent_In verilog.py in the printinit function, the instances input are not initialized09:54
_florent_but it's maybe something that would be solved with what you suggested09:55
lekernelah, that's a bug09:56
lekernelbut I'm actually refactoring that code right now, and that problem should be solved09:56
lekerneland yes the function option would resolve this as well09:56
_florent_ok so I will try to change my module to functions09:58
lekernelthe original bug that refactoring was supposed to solve is you cannot use Array() in Instance expressions09:58
_florent_ok09:59
lekernelso you doing the HDMI out?10:00
_florent_thanks for the advices10:00
_florent_i'm trying to use the ADV7511 on the KC70510:00
lekernelmaybe you should put all the functions in a single Python module, so you don't have too many imports and files10:01
_florent_but it's not working for the moment10:01
lekernelah10:01
_florent_I have to do simulation10:01
lekernelI wonder why they added that chip10:01
lekernelkintex 7 io can do TMDS, no?10:01
lekernelmaybe for 225MHz (2250Gbps data rate, iirc k7 can only do 1800)? I wonder why FPGA vendors only seem to be able to make only slow IOs, even in 28nm devices :(10:03
_florent_I don't know about TDMS on kintex710:03
lekernels/Gbps/Mbps10:03
_florent_yes I remember that for the DDR the IOs were limited to 1800 or 160010:04
_florent_for the moment I'm trying to figure how to configure the ADV7511... don't seems to be easy10:05
_florent_but that's a spare time project so I'm not going very fast...10:06
lekernelhow about hooking up a HDMI cable to the IO expansion header and driving TMDS directly?10:06
lekernelthis way you don't depend on some proprietary chip10:06
_florent_I'm waiting for your HDMI extension to work and after that why not ;) !10:07
lekernelDVI signaling is a mere 8b10b encoding of the VGA samples10:07
lekernelI'm doing a HDMI receiver... there won't be much, if anything, in common10:08
_florent_ah ok10:08
_florent_I was thinking i was doing both10:08
_florent_after the ADV7511 configuration I will need a ddr controller...10:10
_florent_but it will be another story10:10
lekernelyou can try it with a generated pattern first10:10
_florent_yes that what I'm planning to do10:11
lekernelmy first vga-out was on a cyclone 2 with no sdram and not even a dac :) just used a few resistors10:11
_florent_the same for me on a altera de110:12
_florent_I have to return to work..10:13
_florent_thanks for the advices10:13
_florent_I will try to use function instead of Module10:13
_florent_bye10:13
lekernelbye!10:14
larsclekernel: the chip was added so we can sell it of course ;)12:28
lekernelyeah I picked that up...12:28
larscbut the same is on all the xilinx boards12:28
lekernelsame for the tmds chip on the atlys I guess12:28
lekernelbut from TI this time12:28
larscthey used TI before but switched to AD for all the newer boards12:29
lekernelat least it has a purpose on the kc705: compensate a bit for the super-slow FPGA IOBs12:29
lekernelon the atlys it's completely useless afaict12:29
lekernelit provides some electrical protection for the FPGA, but you could do the same with TVS diodes12:30
larscgot a sick-note for the next two weeks, so lots of time for migen hacking ;)12:34
Fallenou:)12:41
lekernelhahaha12:43
lekernelbtw it would be great to get migen presented at http://www.ohwr.org/projects/ohr-meta/wiki/OHW2013 - I'm very far from SF at that date (30+ hrs air travel) :/12:43
lekernelI can contribute to the travel costs if that helps...12:47
Fallenouif they pay for the ride it can help to make up someone's mind :)12:47
Fallenouhave you asked Florent K. ?12:48
lekernelnot yet12:49
GitHub117[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/xP7vPA13:39
GitHub117migen/master e95d2f4 Sebastien Bourdeauducq: fhdl/tools/value_bits_sign: support not13:39
GitHub117migen/master dc55289 Sebastien Bourdeauducq: fhdl/tools/_ArrayLowerer: complete support for arrays as targets13:39
GitHub50[milkymist-ng] sbourdeauducq pushed 5 new commits to master: http://git.io/Npb_1A18:03
GitHub50milkymist-ng/master 3a0cf27 Sebastien Bourdeauducq: dvisampler: fixes18:03
GitHub50milkymist-ng/master 621526f Sebastien Bourdeauducq: dvisampler/datacapture: fix tap counter reg18:03
GitHub50milkymist-ng/master 74cc045 Sebastien Bourdeauducq: dvisampler/datacapture: connect IODELAY IOCLK018:03
GitHub122[mibuild] sbourdeauducq pushed 1 new commit to master: http://git.io/0Lkxhw18:03
GitHub122mibuild/master 797411c Sebastien Bourdeauducq: generic_platform: do not create clock domains during Verilog conversion18:03
GitHub140[migen] sbourdeauducq pushed 3 new commits to master: http://git.io/GpZiPg18:03
GitHub140migen/master 7a06e94 Sebastien Bourdeauducq: Lowering of Special expressions + support ClockSignal/ResetSignal18:03
GitHub140migen/master af4eb02 Sebastien Bourdeauducq: examples/basic/arrays: demonstrate lowering of Array in Instance expression18:03
GitHub140migen/master 17f2b17 Sebastien Bourdeauducq: fhdl/verilog: optionally disable clock domain creation18:03
GitHub168[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/KIitRQ18:04
GitHub168milkymist-ng/master 5126f61 Sebastien Bourdeauducq: dvisampler: use pix5x as IODELAY clock18:04
GitHub73[qemu] mwalle created for-upstream (+607 new commits): https://github.com/mwalle/qemu/compare/40475087a5ee^...b1e5fff4afd018:45
GitHub73qemu/for-upstream 4047508 Paolo Bonzini: test-i386: QEMU_PACKED is not defined here...18:45
GitHub73qemu/for-upstream 1b99f83 Paolo Bonzini: test-i386: make it compile with a recent gcc...18:45
GitHub73qemu/for-upstream 93ab25d Paolo Bonzini: target-i386: use OT_* consistently...18:45
GitHub166[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/MB6nUQ19:33
GitHub166milkymist-ng/master 28cb970 Sebastien Bourdeauducq: dvisampler/clocking: proper pix5x reset synchronization19:33
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