| azonenberg | lekernel: So IDK if i mentioned but i'm writing a F/OSS toolchain for coolrunner-ii CPLDs | 05:34 |
|---|---|---|
| azonenberg | i figure i'll let wolfspraul and company work on spartan6, thats a nice goal but is a huge undertaking | 05:34 |
| azonenberg | CR-II is small enough to actually be tractable for a one-man operation | 05:34 |
| azonenberg | I have the bitstream structure largely reversed and am able to load them into memory and serialize back to disk, then load the resulting image onto the chip | 05:35 |
| azonenberg | there's a handful of fields i haven't figured out (like a dozen 2-input muxes and one part of the crossbar) but another few hours of work is all that will take | 05:35 |
| azonenberg | then i can work on a place-and-route setup | 05:35 |
| azonenberg | xiangfu: did you miss what i just said about the CPLD stuff? | 05:46 |
| xiangfu | yes. I miss that. | 05:46 |
| azonenberg | (00:35:13) azonenberg: I have the bitstream structure largely reversed and am able to load them into memory and serialize back to disk, then load the resulting image onto the chip | 05:46 |
| azonenberg | (00:35:38) azonenberg: there's a handful of fields i haven't figured out (like a dozen 2-input muxes and one part of the crossbar) but another few hours of work is all that will take | 05:46 |
| azonenberg | (00:35:49) azonenberg: then i can work on a place-and-route setup | 05:46 |
| azonenberg | i did a test an hour ago of taking an object-oriented in-memory representation of a design (loaded from an ISE-generated bitstream), serializing to a bitstream, then loading onto the chip | 05:47 |
| azonenberg | at this point it's just figuring out which 2-bit value for a mux corresponds to which of the input choices, etc | 05:47 |
| digshadow | I was thinking of trying to help wolfspraul out on his project but I haven't seen him online for a while, is there another way to contact him | 05:52 |
| lekernel | digshadow, pull requests? ;) | 07:38 |
| azonenberg | he does have the stuff on github but i havent looked at it much | 07:39 |
| azonenberg | been busy with the CPLDs | 07:39 |
| azonenberg | thats a separate codebase since the architecture has basically nothing in common | 07:39 |
| lekernel | azonenberg, sounds cool! | 07:39 |
| azonenberg | lekernel: it appears XC2C has only one bit per IO bank for input and one for output standard | 07:39 |
| azonenberg | low range (LVCMOS18/LVCMOS15) and high (LVCMOS33/LVCMOS25/LVTTL) | 07:40 |
| azonenberg | the detailed standard values affect timing analysis but not the bitstream | 07:40 |
| digshadow | pull request did cross my mind actually :P | 07:48 |
| roh | azonenberg: cool stuff. looking forward to play with it. | 09:37 |
| roh | heh. seems most xbox360 modchips are based on coolrunner2 *g* | 09:39 |
| azonenberg | roh: lol | 09:39 |
| azonenberg | Give me 5 mins and i'll pastebin some output | 09:40 |
| roh | and its 2E per chip from the first piece | 09:40 |
| azonenberg | Yeah | 09:40 |
| azonenberg | I'm only supporting XC2C32A for now but the code will scale to other stuff too | 09:41 |
| roh | XC2C64A-7VQG44C is what i looked up | 09:41 |
| roh | thats 1 euro .. wow. | 09:41 |
| azonenberg | Yeaj | 09:41 |
| azonenberg | xc2c32a is $1.20 in the US for the cheapest package/speed | 09:42 |
| azonenberg | only ~750 gate equivalents and 32 flipflops | 09:42 |
| azonenberg | but still, *any* programmable logic with a F/OSS toolchain is a lot better than none | 09:42 |
| roh | still quite a desk full of ttl/cmos parts without programmable logic | 09:42 |
| roh | true. will be quite a nice companion for small mcu | 09:42 |
| azonenberg | I'm just confused as to what is going on with the xilinx toolchain | 09:44 |
| azonenberg | going from an in-memory bitstream image for the CPLD to a ROM image takes them 1.6 seconds | 09:44 |
| azonenberg | my code at the moment runs in 40ms | 09:44 |
| azonenberg | either i'm missing something or they did something really dumb | 09:44 |
| azonenberg | i'm not far enough along yet to know which | 09:45 |
| roh | ah. dont wonder. i guess the latter | 09:45 |
| azonenberg | Lol | 09:45 |
| roh | but maybe there is some sideeffect they want to avoid/check for which isnt even important for that chip, which takes a lot of calculations. | 09:45 |
| azonenberg | a strace shows that they load 85KB of XML with static timing analysis info | 09:46 |
| azonenberg | that process has no output | 09:46 |
| roh | but its in the chain.... thousands of things can go weird withn big companies, their toolchains and no proper documentation | 09:46 |
| azonenberg | and runs on a netlist that's already placed and routd | 09:46 |
| azonenberg | Lol, yes | 09:46 |
| roh | i guess half the cpupower on this planet is wasted by stupid coders and business decisions. more on the latter than the first | 09:47 |
| azonenberg | Lol | 09:47 |
| azonenberg | The second | 09:47 |
| azonenberg | that screams "java" to me | 09:47 |
| roh | i thought so too.. but now i know tha java has a real usecase. | 09:48 |
| roh | imagine all these workless drones.... | 09:48 |
| azonenberg | Lol | 09:48 |
| azonenberg | roh: http://pastebin.com/raw.php?i=PkJnMYK3 | 09:48 |
| azonenberg | This is my code to date running on an XC2C32A bitstream consisting of the single verilog line "assign dout = ~din" | 09:49 |
| azonenberg | din is LVCMOS33 on pin 28 and dout is LVCMOS33 on pin 38 | 09:49 |
| roh | flying crowbar? nice name :) like it | 09:49 |
| azonenberg | Lol | 09:53 |
| azonenberg | The *s in the arrays mean there's a connection, a space means no connection | 09:53 |
| azonenberg | Drawing a NOT gate in UTF-8 is a pain in the neck :P | 09:53 |
| roh | hrhr | 09:53 |
| azonenberg | Notice a lot of the fiedls are still numeric values | 09:54 |
| azonenberg | fields* | 09:54 |
| azonenberg | rather than descriptive names | 09:54 |
| azonenberg | Those are the ones i have not yet figured out | 09:54 |
| roh | well.. seems like details to me.. you'll figure it out | 09:54 |
| azonenberg | Yes | 09:54 |
| roh | great work anyhow. i'm impressed | 09:54 |
| azonenberg | I am quite confident i will have the structure mostly figured out by the end of the weekend | 09:54 |
| azonenberg | The next step will be to take the library and start building a place-and-route tool in front of it (given an optimized, unplaced netlist and constraints) | 09:55 |
| azonenberg | Then I can decide whther to try to adapt iverilog to be a front end or try to roll my own | 09:55 |
| roh | do you think going up and down the model chain will change much? | 09:55 |
| azonenberg | One design decision is final already | 09:55 |
| azonenberg | I am not going GPL | 09:55 |
| azonenberg | BSD license | 09:55 |
| azonenberg | The only reason for GPL is to prevent third parties from stealing your work and turning it into a proprietary product | 09:56 |
| roh | well.. no problem. as long as its a foss licence and not something stupid like cddl ;) | 09:56 |
| azonenberg | nobody but xilinx would have any reason to do that | 09:56 |
| azonenberg | and xilinx has a full-time team of programmers working on this | 09:56 |
| azonenberg | they don't need my spare-time project :p | 09:56 |
| roh | azonenberg: you think... well... all the current xilinx stuff was some other companies before | 09:56 |
| azonenberg | This entire codebase, btw, was the work of two or three days | 09:56 |
| azonenberg | roh: also, the bigger thing | 09:56 |
| azonenberg | why would anyone pay for their fork when mine is open source and costs nothing :p[ | 09:57 |
| azonenberg | If they end up merging my code into their product i wouldn't complain | 09:57 |
| azonenberg | i'd be honored | 09:57 |
| lekernel | azonenberg, how far are you from verilog/vhdl-style synthesis? | 09:57 |
| azonenberg | lekernel: I'm not even touching that | 09:57 |
| roh | i usually do whats best for the project. if its bsd i do bsd, if its gpl i do gpl. if its nothing yet i use gpl since i want people who use it commercially to either do it opensource or pay me. | 09:57 |
| azonenberg | Right now what i'm doing is compiling simple dummy designs and manipulating them | 09:57 |
| lekernel | what's the interface to the chip you have then? | 09:57 |
| roh | azonenberg: fork means 'it stays open' .. thats not what happens when companies use bsd code. | 09:58 |
| azonenberg | roh: they'd make a private fork and commercialize it, sure | 09:58 |
| azonenberg | But it won't stop this version from being useful | 09:58 |
| azonenberg | So i really don't care | 09:58 |
| lekernel | direct migen/fhdl-to-cpld sounds sexy and pretty low-hanging | 09:58 |
| azonenberg | lekernel: XST -> cpldfit -> hprep6 -> JED file is the normal workflow | 09:58 |
| azonenberg | My library can do JED -> in-memory image | 09:59 |
| azonenberg | in-memory image -> JED | 09:59 |
| azonenberg | and in-memory image -> programmed CPLD | 09:59 |
| roh | azonenberg: well.. thats where we differ ;) i like to keep free stuff free. i see it as a step back. but i respect such decisions. | 09:59 |
| azonenberg | what i'm working on now is making the in-memory image be intellegible | 09:59 |
| azonenberg | rather than say a variable called "fb" with the value 3, which is pretty meaningless | 10:00 |
| roh | gotta run.. bbl | 10:00 |
| azonenberg | so basically creating enums for all of the muxes | 10:00 |
| azonenberg | figuring out how the interconnect matrix works | 10:00 |
| azonenberg | etc | 10:00 |
| lekernel | and what interface will we have once this is done? | 10:00 |
| azonenberg | The next step will be to use the C++ API i have now as the underlying framework for a place-and-route tool | 10:00 |
| lekernel | C++? urgh | 10:00 |
| lekernel | why not plain C? | 10:01 |
| azonenberg | Objects fit very nicely for what i'm doing | 10:01 |
| azonenberg | I could make a C front end to the PAR tool i guess | 10:01 |
| lekernel | use python, lua, ruby, etc. then | 10:01 |
| azonenberg | anyway, you'd synthesize to some kind of equation format and then feed that to the PAR tool | 10:01 |
| lekernel | C++ is a hateful language | 10:02 |
| azonenberg | I've written enough C++ i've grown to like it | 10:02 |
| azonenberg | But you have to use it carefully | 10:02 |
| azonenberg | i dont go all-out with crazy stuff | 10:02 |
| azonenberg | i usually treat it as C with the ability to put functions in structs :p | 10:02 |
| lekernel | then why not write C with functions in structs? :) | 10:02 |
| azonenberg | Because the syntactic sugar increases my productivity | 10:03 |
| azonenberg | don't like it, fork my code :P | 10:03 |
| azonenberg | or write a wrapper | 10:03 |
| azonenberg | Example JED file from the Xilinx toolchain (what my app generated that visualization from) http://pastebin.com/8pQgE7j3 | 10:04 |
| azonenberg | Output from my tool (syntactically equivalent but pretty-printed) http://pastebin.com/3bdezXyu | 10:04 |
| azonenberg | Oh, and at some point in the pipeline I need to do static timing analysis | 10:06 |
| azonenberg | The big thing about C++ that i use in this code is inheritance, in some cases multiple | 10:09 |
| azonenberg | that's mostly in the JTAG HAL library though, not the bitstream stuff | 10:10 |
| azonenberg | libcrowbar links to libjtaghal but libjtaghal can be used standalone as well | 10:10 |
| azonenberg | lekernel: at some point i would eventually (i dont have the time now) make a behavioral model of the xc2c32a | 10:14 |
| azonenberg | it will be theoretically synthesizeable but use a huge number of FFs and likely not meet timing | 10:14 |
| azonenberg | http://pastebin.com/raw.php?i=zvtj7U8U :) | 11:54 |
| azonenberg | Figured out FF edge triggering | 11:54 |
| azonenberg | Ten more fields to figure out, a couple of which are already mostly reversed but not quite fully | 11:54 |
| azonenberg | then global interconnect and i'm done | 11:54 |
| --- Sun Feb 3 2013 | 00:00 | |
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