#milkymist IRC log for Saturday, 2013-02-02

azonenberglekernel: So IDK if i mentioned but i'm writing a F/OSS toolchain for coolrunner-ii CPLDs05:34
azonenbergi figure i'll let wolfspraul and company work on spartan6, thats a nice goal but is a huge undertaking05:34
azonenbergCR-II is small enough to actually be tractable for a one-man operation05:34
azonenbergI have the bitstream structure largely reversed and am able to load them into memory and serialize back to disk, then load the resulting image onto the chip05:35
azonenbergthere's a handful of fields i haven't figured out (like a dozen 2-input muxes and one part of the crossbar) but another few hours of work is all that will take05:35
azonenbergthen i can work on a place-and-route setup05:35
azonenbergxiangfu: did you miss what i just said about the CPLD stuff?05:46
xiangfuyes. I miss that.05:46
azonenberg(00:35:13) azonenberg: I have the bitstream structure largely reversed and am able to load them into memory and serialize back to disk, then load the resulting image onto the chip05:46
azonenberg(00:35:38) azonenberg: there's a handful of fields i haven't figured out (like a dozen 2-input muxes and one part of the crossbar) but another few hours of work is all that will take05:46
azonenberg(00:35:49) azonenberg: then i can work on a place-and-route setup05:46
azonenbergi did a test an hour ago of taking an object-oriented in-memory representation of a design (loaded from an ISE-generated bitstream), serializing to a bitstream, then loading onto the chip05:47
azonenbergat this point it's just figuring out which 2-bit value for a mux corresponds to which of the input choices, etc05:47
digshadowI was thinking of trying to help wolfspraul out on his project but I haven't seen him online for a while, is there another way to contact him05:52
lekerneldigshadow, pull requests? ;)07:38
azonenberghe does have the stuff on github but i havent looked at it much07:39
azonenbergbeen busy with the CPLDs07:39
azonenbergthats a separate codebase since the architecture has basically nothing in common07:39
lekernelazonenberg, sounds cool!07:39
azonenberglekernel: it appears XC2C has only one bit per IO bank for input and one for output standard07:39
azonenberglow range (LVCMOS18/LVCMOS15) and high (LVCMOS33/LVCMOS25/LVTTL)07:40
azonenbergthe detailed standard values affect timing analysis but not the bitstream07:40
digshadowpull request did cross my mind actually :P07:48
rohazonenberg: cool stuff. looking forward to play with it.09:37
rohheh. seems most xbox360 modchips are based on coolrunner2 *g*09:39
azonenbergroh: lol09:39
azonenbergGive me 5 mins and i'll pastebin some output09:40
rohand its 2E  per chip from the first piece09:40
azonenbergYeah09:40
azonenbergI'm only supporting XC2C32A for now but the code will scale to other stuff too09:41
roh XC2C64A-7VQG44C is what i looked up09:41
rohthats 1 euro .. wow.09:41
azonenbergYeaj09:41
azonenbergxc2c32a is $1.20 in the US for the cheapest package/speed09:42
azonenbergonly ~750 gate equivalents and 32 flipflops09:42
azonenbergbut still, *any* programmable logic with a F/OSS toolchain is a lot better than none09:42
rohstill quite a desk full of ttl/cmos parts without programmable logic09:42
rohtrue. will be quite a nice companion for small mcu09:42
azonenbergI'm just confused as to what is going on with the xilinx toolchain09:44
azonenberggoing from an in-memory bitstream image for the CPLD to a ROM image takes them 1.6 seconds09:44
azonenbergmy code at the moment runs in 40ms09:44
azonenbergeither i'm missing something or they did something really dumb09:44
azonenbergi'm not far enough along yet to know which09:45
rohah. dont wonder. i guess the latter09:45
azonenbergLol09:45
rohbut maybe there is some sideeffect they want to avoid/check for which isnt even important for that chip, which takes a lot of calculations.09:45
azonenberga strace shows that they load 85KB of XML with static timing analysis info09:46
azonenbergthat process has no output09:46
rohbut its in the chain.... thousands of things can go weird withn big companies, their toolchains and no proper documentation09:46
azonenbergand runs on a netlist that's already placed and routd09:46
azonenbergLol, yes09:46
rohi guess half the cpupower on this planet is wasted by stupid coders and business decisions. more on the latter than the first09:47
azonenbergLol09:47
azonenbergThe second09:47
azonenbergthat screams "java" to me09:47
rohi thought so too.. but now i know tha java has a real usecase.09:48
rohimagine all these workless drones....09:48
azonenbergLol09:48
azonenbergroh: http://pastebin.com/raw.php?i=PkJnMYK309:48
azonenbergThis is my code to date running on an XC2C32A bitstream consisting of the single verilog line "assign dout = ~din"09:49
azonenbergdin is LVCMOS33 on pin 28 and dout is LVCMOS33 on pin 3809:49
rohflying crowbar? nice name :) like it09:49
azonenbergLol09:53
azonenbergThe *s in the arrays mean there's a connection, a space means no connection09:53
azonenbergDrawing a NOT gate in UTF-8 is a pain in the neck :P09:53
rohhrhr09:53
azonenbergNotice a lot of the fiedls are still numeric values09:54
azonenbergfields*09:54
azonenbergrather than descriptive names09:54
azonenbergThose are the ones i have not yet figured out09:54
rohwell.. seems like details to me.. you'll figure it out09:54
azonenbergYes09:54
rohgreat work anyhow. i'm impressed09:54
azonenbergI am quite confident i will have the structure mostly figured out by the end of the weekend09:54
azonenbergThe next step will be to take the library and start building a place-and-route tool in front of it (given an optimized, unplaced netlist and constraints)09:55
azonenbergThen I can decide whther to try to adapt iverilog to be a front end or try to roll my own09:55
rohdo you think going up and down the model chain will change much?09:55
azonenbergOne design decision is final already09:55
azonenbergI am not going GPL09:55
azonenbergBSD license09:55
azonenbergThe only reason for GPL is to prevent third parties from stealing your work and turning it into a proprietary product09:56
rohwell.. no problem. as long as its a foss licence and not something stupid like cddl ;)09:56
azonenbergnobody but xilinx would have any reason to do that09:56
azonenbergand xilinx has a full-time team of programmers working on this09:56
azonenbergthey don't need my spare-time project :p09:56
rohazonenberg: you think... well... all the current xilinx stuff was some other companies before09:56
azonenbergThis entire codebase, btw, was the work of two or three days09:56
azonenbergroh: also, the bigger thing09:56
azonenbergwhy would anyone pay for their fork when mine is open source and costs nothing :p[09:57
azonenbergIf they end up merging my code into their product i wouldn't complain09:57
azonenbergi'd be honored09:57
lekernelazonenberg, how far are you from verilog/vhdl-style synthesis?09:57
azonenberglekernel: I'm not even touching that09:57
rohi usually do whats best for the project. if its bsd i do bsd, if its gpl i do gpl. if its nothing yet i use gpl since i want people who use it commercially to either do it opensource or pay me.09:57
azonenbergRight now what i'm doing is compiling simple dummy designs and manipulating them09:57
lekernelwhat's the interface to the chip you have then?09:57
rohazonenberg: fork means 'it stays open' .. thats not what happens when companies use bsd code.09:58
azonenbergroh: they'd make a private fork and commercialize it, sure09:58
azonenbergBut it won't stop this version from being useful09:58
azonenbergSo i really don't care09:58
lekerneldirect migen/fhdl-to-cpld sounds sexy and pretty low-hanging09:58
azonenberglekernel: XST -> cpldfit -> hprep6 -> JED file is the normal workflow09:58
azonenbergMy library can do JED -> in-memory image09:59
azonenbergin-memory image -> JED09:59
azonenbergand in-memory image -> programmed CPLD09:59
rohazonenberg: well.. thats where we differ ;) i like to keep free stuff free. i see it as a step back. but i respect such decisions.09:59
azonenbergwhat i'm working on now is making the in-memory image be intellegible09:59
azonenbergrather than say a variable called "fb" with the value 3, which is pretty meaningless10:00
rohgotta run.. bbl10:00
azonenbergso basically creating enums for all of the muxes10:00
azonenbergfiguring out how the interconnect matrix works10:00
azonenbergetc10:00
lekerneland what interface will we have once this is done?10:00
azonenbergThe next step will be to use the C++ API i have now as the underlying framework for a place-and-route tool10:00
lekernelC++? urgh10:00
lekernelwhy not plain C?10:01
azonenbergObjects fit very nicely for what i'm doing10:01
azonenbergI could make a C front end to the PAR tool i guess10:01
lekerneluse python, lua, ruby, etc. then10:01
azonenberganyway, you'd synthesize to some kind of equation format and then feed that to the PAR tool10:01
lekernelC++ is a hateful language10:02
azonenbergI've written enough C++ i've grown to like it10:02
azonenbergBut you have to use it carefully10:02
azonenbergi dont go all-out with crazy stuff10:02
azonenbergi usually treat it as C with the ability to put functions in structs :p10:02
lekernelthen why not write C with functions in structs? :)10:02
azonenbergBecause the syntactic sugar increases my productivity10:03
azonenbergdon't like it, fork my code :P10:03
azonenbergor write a wrapper10:03
azonenbergExample JED file from the Xilinx toolchain (what my app generated that visualization from) http://pastebin.com/8pQgE7j310:04
azonenbergOutput from my tool (syntactically equivalent but pretty-printed) http://pastebin.com/3bdezXyu10:04
azonenbergOh, and at some point in the pipeline I need to do static timing analysis10:06
azonenbergThe big thing about C++ that i use in this code is inheritance, in some cases multiple10:09
azonenbergthat's mostly in the JTAG HAL library though, not the bitstream stuff10:10
azonenberglibcrowbar links to libjtaghal but libjtaghal can be used standalone as well10:10
azonenberglekernel: at some point i would eventually (i dont have the time now) make a behavioral model of the xc2c32a10:14
azonenbergit will be theoretically synthesizeable but use a huge number of FFs and likely not meet timing10:14
azonenberghttp://pastebin.com/raw.php?i=zvtj7U8U :)11:54
azonenbergFigured out FF edge triggering11:54
azonenbergTen more fields to figure out, a couple of which are already mostly reversed but not quite fully11:54
azonenbergthen global interconnect and i'm done11:54
--- Sun Feb 3 201300:00

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