#milkymist IRC log for Wednesday, 2013-01-23

--- Wed Jan 23 201300:00
larscsb0: how is cape town?12:18
sb0sunny, it's 30C here12:18
wpwrakadding a bit of vacation after the conference ?12:52
sb0no, I fly back on the 31st... looking forward to a nice hiking/urbex/bbq weekend though13:10
sb0tomorrow is another day at the SKA office, and more Migen pitching there - would be nice to get more contribs13:13
sb0pretty much everyone there hates EDK and Simulink that a Migen-based solution could nicely replace, but they love legacy code...13:14
wpwraklegacy is always a bit problem. lots and lots of inertia ...13:18
sb0after I'm back I should have more time to work on M3 and video mixing... now that I no longer have major distractions like EHSM...13:19
sb0would be nice if Florent gets the DDR3 to work on kintex-713:19
Fallenousb0: have you fixed the bug in migen.fhdl.verilog in convert() that outputs different verilog code when calling several times convert()?13:34
Fallenouadding sys_clk1 sys_clk2 etc13:34
sb0not yet13:34
sb0haven't looked at it13:35
Fallenouok np13:35
FallenouI did a "private session" (rattrapage) of the migen workshop for Alarm in mp13:35
sb0it's on my list ...13:35
Fallenouand we hit that bug as well13:35
Fallenouhum, it's the call to ios.add()13:43
Fallenoueach time it adds a new io for clk and rst13:43
Fallenouhum not sure ...13:45
sb0ah yes13:56
sb0let me try...13:56
GitHub59[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/3201554f7646e8cbd007124104ee5198a1dbb83d14:00
GitHub59migen/master 3201554 Sebastien Bourdeauducq: fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()14:00
sb0should be fixed now, thanks for the hint14:01
sb0Fallenou, is the problem gone?14:12
FallenouI don't know, I'm at the office right now, I will try at home and I will quickly let you know :)14:16
Fallenouthanks for the quick commit14:17
Fallenousb0: it seems fixed now :)14:21

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