#milkymist IRC log for Tuesday, 2013-01-08

azonenberglekernel: so i see you saw my FB status12:26
azonenbergWhat are you guys doing for in-circuit debug, if anything?12:26
azonenbergboth hardware and software12:26
azonenberglekernel: also if i want to cite migen in a paper i'm working on, do you have a specific paper/article etc that i should reference?12:32
azonenbergA BibTeX citation would be desirable if possible ;)12:32
lekernelazonenberg, hmm, http://milkymist.org/3/migen.html or http://milkymist.org/3/migen.pdf13:34
lekernelI haven't written a proper academic paper yet I'm afraid...13:34
azonenberglekernel: ok13:34
azonenbergI'm doing some work on NoC for my thesis and am thinking of exploring methods of automatically generating optimal topologies from activity traces13:34
lekernelthere isn't much in-circuit debug, just some debug cores that can be mapped to the CPU bus13:34
azonenbergso i'm looking for prior examples of programmatically generating bus/NoC topology13:35
azonenbergAnd I see, i'm trying to get something a little more involved13:35
azonenbergDo you guys do hardware cosimulation at all?13:35
lekernelnot yet13:36
azonenbergYou guys would love the stuff i'm developing then13:36
azonenbergi need another month or so to get it to the point that it's usable13:36
azonenbergAnd i'm not sure how hard it would be to port it to wishbone since a few of the modules have hard-coded my NoC frame structure13:36
azonenbergBut basically I make a VPN into the NoC from my PC13:37
azonenbergand then am able to send NoC frames to any core on the chip over TCP sockets13:37
azonenbergFrom any application on my laptop including but not limited to a bridge that talks to ISim13:37
azonenbergi have a verilog core that pretends to be a NoC router and sends frames to the nocswitch binary which then forwards over jtag to the board13:38
azonenbergall of the routing just works because of the hierarchal address space, the simulated stuff just shows up as another block of address space13:38
azonenbergAnd since the NoC is multimaster i can then send traffic to any core on the bus from it13:38
azonenbergSo I could code up a quick testbench, run it in the simulator, have it send messages to real hardware, and print everything that goes between them13:39
lekernelazonenberg, btw, any luck with coaxing ACM into putting your paper into the public domain?13:39
azonenbergI haven't submitted anything yet13:39
azonenbergI'm putting most of my effort now into a survey paper13:40
azonenbergBoth because it's my research qualifying exam, and because it will give me a better idea of prior work related to what i'm doing13:40
lekernelthey're pestering me with unfriendly copyright forms and email requests atm, and I'm wondering what is the most efficient way to deal with those13:40
azonenbergoh joy13:41
azonenbergSubmit to another journal instead? :P13:41
azonenbergalso, yay - my issue tracker has <50 tickets on it for the first time in a week :D13:42
azonenbergopen, that is13:42
wpwraklekernel: at EPFL, we made a technical report from each paper we submitted to a conference/journal. the TR had different formatting and usually contained a bit more material. the TRs were openly available. nobody ever complained :)13:47
azonenbergSo you let them claim the rights to the paper and then you publish the TR13:48
azonenbergmake the TR slightly more in-depth13:48
lekernelI have selected "I'm a US govt employee" in their automatic system so that their sneaky javascript-based form made the "public domain" checkbox appear, unfortunately, someone noticed13:48
wpwrakoh, the TR usually went out first. papers can take forever before they appear.13:48
azonenbergand the journal can hardly complain about you releasing your future work13:49
azonenbergwhat i mean is, by making the TR look like it came after the paper13:49
lekernelwpwrak, http://www.r6.ca/blog/20110930T012533Z.html13:49
azonenbergthe journal can't complain about you publishing work you did "after" the paper that happens to include some of the old material13:49
lekernelwpwrak, they have the "no more need to publish it" answer for those cases, so be careful13:49
lekernel"I replied to ACM legal explaining that I have put a copy of my publication on the arXiv under a public domain dedication and therefore I was unable to transfer copyright to them. ACM legal replied, I understand that you have placed your paper in the public domain and on the arXiv site. It is therefore considered as published and there is no need for ACM to republish it in the WGP proceedings."13:50
wpwrakazonenberg: naw, no need to go extremes trying to hide things. there's not much of a conflict anyway. the IEEE/Springer/Elsevier/etc. publications have their role for scoring anyway. it's only now that this is changing13:50
wpwraklekernel: well, it's not the SAME paper ;-)13:51
azonenbergyeah, that's the tricky part13:51
azonenbergnot being the same thing13:51
wpwrakthat's easy. starts with the formatting (which tends to require small content adaptations, too). and you often have size limits on journal/conference papers, so you end up trimming it anyway.13:53
azonenbergYeah, adding new content is to me the biggest thing that makes the TR different13:53
wpwrakand you make have stuff like measurements that you'd never put into a journal but that doesn't get in the way if you put it into a TR13:53
wpwrakso unless the publisher is actively looking for a fight, there's enough plausible deniability to avoid conflict13:55
azonenbergThe big thing is, it would be seen as unreasonable for them to prohibit you from publishing a TR based on work you did after the journal paper was submitted13:56
azonenbergand it's expected that you'd include your earlier work for background13:56
lekernelis there anyone who sees their current download fees as reasonable?13:56
azonenberglegally it's still a copyright gray area, especially if you re-use figures etc13:56
azonenbergI have free access through my school but the numbers i see are absurd13:57
wpwrakwork done later, definitely. but i think the same goes for any work that's not in the paper, also if done before.13:57
azonenberg$20+ for one paper13:57
lekernelyeah and your school library is paying through the nose for the subscriptions13:57
azonenberglekernel: oh, i believe it13:57
azonenbergSo far my only cited paper has never been published in such a journal13:57
azonenbergi just posted it on my own website and people found it13:57
wpwrakheh, my most successful paper, according to citeseer: "Linux Network Traffic Control - Implementation Overview (1999)"14:04
wpwrakand people say academics have no sense for the practical :)14:04
azonenbergi am a very applied person too14:05
azonenbergBut I like to do pure applications and not waste time with such frivolities as how to make money with it14:05
azonenbergwhich most companies sadly seem to put as their first priority14:06
azonenbergthe world needs more nonprofit R&D labs14:06
wpwrakindeed !14:07
azonenbergMy first priority is "solve $PROBLEM as well as i possibly can"14:07
azonenbergnot "solve $PROBLEM well enough to meet the needs of 70-80% of our potential customer base, at the minimum cost, while doing just enough work that they don't demand refunds"14:08
wpwrakwe should be compensated for the damage we're not doing. after all, bright fellows like us could also have gone into finance and cooked up some novel ruinous bubble-production schemes14:08
azonenbergOr built a nuclear device :P14:08
azonenbergIf all of the bored engineers in the world got together we could probably build a small nuke in a few years' time14:09
wpwrakbreed black holes at CERN14:10
wpwrak"a few years" ? c'mon14:10
azonenbergi'm actually idly curious about that14:11
azonenbergthere are all kinds of nonproliferation treaties restricting what you can export14:11
azonenbergBut i suspect if a group within say the USA decided to build a nuke from domestic parts it would be a lot easier :P14:11
azonenbergBack to on-topic stuff14:12
azonenbergi've been noticing an annoying problem with kicad, it always puts a pad around a via on every layer14:12
lekernelaha, we could have had He-3 at EHSM ;)14:12
azonenbergeven if you are not connecting to it14:12
azonenbergWhich means if I have a via from top to bottom, an inner layer trace has to stay (annular ring + clearance) away from it14:13
lekernelhopefully we'll have dilution refrigerators and things like that at some future edition14:13
azonenberglekernel: maybe i can make it to the next one in person14:13
azonenberghow did john's talk go?14:13
larscIn my opinion it was very well done14:14
lekernelI had to take care of the conference cash desk and missed it :(14:14
azonenberglekernel: :(14:15
azonenbergBTW idk if i mentioned before in here but i was looking at the coolrunner-ii CPLDs14:15
azonenbergas a side project in parallel with fpgatools14:15
lekernelI still need to watch the video ...14:15
azonenbergthey're about the cheapest programmable logic around (at least for the small like 32 macrocell units)14:15
azonenbergthe bitstreams are tiny14:16
azonenbergAnd the JED files xilinx tools generate have comments in them :D14:16
azonenbergthey partition the fuses into the AND array, the OR array, the interconnect, global clock, etc14:16
azonenbergI feel like once i have time to sit down and play with it i could probably bang out a basic compiler in a few weeks14:16
azonenbergat most14:16
azonenbergwolfgang's work is all well and good for high-capacity stuff but CR-II is something i think we could feasibly have a full FOSS toolchain for pretty quickly14:17
azonenberglibjtaghal can already program spartan-6 and as soon as a board i designed (currently at the fab) with an FT232H and XC2C32A is done i will write a CR-II bitstream loader module for it14:19
azonenbergSo we could have a full end-to-end FOSS toolchain for *a* currently shipping programmable logic device14:19
azonenbergEven if it is just a 32-macrocell CPLD (with eventual scaling to larger devices)14:20
azonenbergi'm debating whether to try writing my own super-simple synthesis tool or try to hack iverilog14:20
azonenbergsince it no longer seems to support synthesis14:20
wpwraka toolchain for CPLDs would be awsome14:20
azonenbergFor the first attempt of course i'll be entering manual sum-of-products expressions by hand in some kind of text file14:20
azonenbergwpwrak: well it's actively in progress14:21
azonenbergi'm going bottom up14:21
azonenbergfirst, load flash images onto the chip (that's waiting on the board)14:21
azonenbergthen, take hand-generated product terms and config settings and make a bitstream14:21
azonenbergthen synthesize verilog to that intermediate represnetation14:21
azonenbergfirst target is XC2C32A, then scaling to larger CR-II devices later on14:22
azonenbergthe 64a is pin compatible in tqfp 44 so i can put it on the same PCB and test it too14:22
wpwrakthe important part is breaking the veil of secrecy14:22
azonenbergthere isnt much with the coolrunners14:22
azonenbergthe arch seems pretty simple and well documented14:22
wpwrakonce you have concept and mapping, people can get to work14:22
azonenbergThe bitstream almost doesn't need reversing14:23
azonenbergThis is what the xilinx tools generate14:23
azonenberglook at that14:23
wpwraksounds perfect. a small price tag is always good.14:23
azonenberg"Block 0 PLA AND array" is a comment in the source14:23
azonenbergthis is the equivalent of a .bit14:24
azonenbergthis is not output from my tools, the compiler generates it14:24
azonenbergAnd each one of those 1s and 0s is directly written to a flash cell14:24
wpwrakstill needs a bit of interpreting :)14:24
azonenbergSure, but not much14:24
azonenbergThe chip starts at $1.20 for the lowest speed grade in single units14:24
wpwrakyeah, could be much worse14:24
azonenbergSo it would be a great stepping stone14:24
azonenbergIt can't share much code with fpgatools since the microarchitecture is so different, unfortunately14:25
wpwrakthough i think the FPGA bitstreams aren't all that different either (at least that's the impression i got from wolfgang's descriptions)14:25
azonenbergFPGA bitstreams you need to start from scratch more since the bit file isnt commented14:25
azonenbergand there are soooo many different types of tile14:25
wpwrakyes, but it's also one bit = one switch or similar14:26
azonenbergthe CPLD is basically a PLA and a bit of global routing14:26
azonenbergand nothign else14:26
azonenbergno ram, no multipliers14:26
wpwrakyeah, CPLDs are simpler :)14:26
azonenbergn oserializers14:26
azonenbergWhich makes it a very attractive first study target14:26
larschow much logic could you fit in there?14:27
azonenberg32 macrocells is the smallest CR-II device14:27
azonenbergeach macrocell is able to implement a sum-of-products expression with up to i think around 56 inputs14:27
azonenbergor is it 40?14:27
azonenbergi have this written down somewhere14:27
azonenbergand then output both directly and throguh a flipflop14:27
wpwrakso only 32 FFs ?14:28
azonenbergin my experience, once you start doing state machines the limiting factor is running out of FFs14:28
azonenbergBut the CR-II line gets bigger14:28
larscand one macrocell is flipflop + lut?14:28
azonenbergthey go up to 512 macrocells14:28
azonenberglarsc: no, they aren't LUT based14:28
azonenbergCPLD microarchitecture is very different14:28
wpwrakgetting better :)14:28
azonenbergit's a big and-or array14:28
azonenbergwpwrak: Those are $$$ though14:28
azonenberg256 is like $2014:28
azonenberg384 and 512 are absurd14:28
azonenbergBut 32/64/128 are relatively cheap14:29
azonenbergthose are my main targets, for glue-logic type applications14:29
azonenbergif you need more than 128 macrocells for your system, go talk to wolfgang :P14:29
azonenbergiirc 256 macrocells is enough to fit a picoblaze CPU14:30
azonenbergor is it 12814:30
azonenbergbut it needs external flash for the program rom i think14:30
wpwrakhmm, for USD 20 you already get three XC6LX9 in china14:30
wpwrakor 1.3 at digi-key14:31
azonenbergIts not cost effective to buy big cplds14:31
azonenbergHence why the small ones are my target14:31
azonenbergxc6slx4/9 start at like $8-1014:31
azonenbergbut you can get 32 / 64 / 128 macrocells of CR-II cheaper14:31
azonenbergand in a nice friendly 0.8mm TQFP for the 32/6414:31
azonenbergnoob friendly14:31
wpwrakXC2C64A seems to be the largest that's still friendly14:34
wpwrakafter that, prices jump and packages get large14:34
wpwrakfor making a very cheap board, a Ben interface (using UBB) may be an attractive option: you have GPIOs for JTAG, the Ben can supply 3.3 V, and it can even supply the clock (up to 56 MHz)14:50
wpwraki don't know if you're reading the qi-hardware list. i already have a proof of concept for JTAG. urtag on the ben talks nicely to the milkymist one :)14:52
kristianpaulazonenberg: Hi, is your NoC related work going or already been public?15:09
Action: kristianpaul want to profit with NoC's at soho level15:10
Fallenou15:13 < azonenberg> how did john's talk go? < it was really good !15:40
azonenbergkristianpaul: will be made public, yes16:42
azonenbergis, no16:42
azonenbergStep 1, debug infrastructure16:47
azonenbergI will be publishing that as well as a survey paper in the spring some time16:47
azonenbergstep 2, build something on top of that16:47
azonenbergWill be published when i finish my thesis16:47
azonenbergthere may be other intermediate steps too16:47
GitHub93[milkymist] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/milkymist/compare/5cec7ea9ce73...7f0313010afd20:52
GitHub93milkymist/master c6509bf Sebastien Bourdeauducq: softusb/navre: use localparam...20:52
GitHub93milkymist/master 7f03130 Sebastien Bourdeauducq: softusb/navre: fix instruction decoder...20:52
GitHub152[lm32] mwalle pushed 2 new commits to master: http://git.io/FxN04g21:16
GitHub152lm32/master e937900 Yann Sionneau: lm32 test Makefiles cleanup...21:16
GitHub152lm32/master 68d407f Yann Sionneau: fix compilation of lm32 tests...21:16
mwallewpwrak: why do you need fjmem?21:26
mwallewpwrak: and whats the use of the breakout board actually?21:28
wpwrak(fjmem) to do through the motions of using urtag on the milkymist. it's just a proof of concept, so i tried to do whatever we do there, to prove that all this works21:50
wpwrakan actual use i have in mind would be for a low-cost fpga/etc. experimentation board21:50
wpwrakbasically the hardware for fpgatools, but without all the overhead of ftdi, oscillator, and so on21:51
wpwrakjust the fpga, one reg for Vcore, a few LEDs, a few headers, done. nanonote can supply 3.3 V, clock, and jtag21:52
--- Wed Jan 9 201300:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!