| lekernel | wpwrak, I have forwarded your email to Adrien | 13:10 |
|---|---|---|
| lekernel | re. wire characterization | 13:10 |
| lekernel | mwalle, yup | 13:10 |
| lekernel | you should have come to the conference mwalle :) | 13:11 |
| wpwrak | lekernel: ah, thanks ! | 13:28 |
| Fallenou | lekernel: ahah nice link, I never go to Quick btw :p | 13:45 |
| Fallenou | even during the star wars burgers sales ... :p | 13:45 |
| wpwrak | Fallenou: they're very efficient in the future. crash a spacecraft ... don't bemoan the dead, have a burgers sale ! kinda like the happy face of soylent green :) | 13:49 |
| Fallenou | wwwwhat ?! | 13:54 |
| Fallenou | please send me samples of what you take :p | 13:54 |
| atgreen | lekernel: watching your migen talk right now - thanks for posting | 13:57 |
| wpwrak | Fallenou: just exploiting the creative phase between waking up and the first dose of caffeine :) | 13:59 |
| Fallenou | wow | 14:02 |
| kyak | lekernel: just watched your video for Migen, very impressive. Since you mentioned dataflow programming, have you seen HDL Coder? (http://www.mathworks.com/products/hdl-coder/) | 14:27 |
| wpwrak | frequency 6000000 -> new real frequency 46570.9, delay 0 operating without delay :) | 14:28 |
| kyak | it has nothing to do with FOSS, of course, but it's a yet another approach from higher level languages to hardware design | 14:28 |
| wpwrak | oops. wrong channel | 14:29 |
| kyak | wpwrak: chaos and confusion! | 14:29 |
| wpwrak | kyak: now you're getting into the spirit :) | 14:30 |
| kyak | we should team up :) | 14:31 |
| wpwrak | yeah. you take the northern hemisphere, i take the south :) | 14:32 |
| kristianpaul | wpwrak: where is your turbo button? :-) | 14:33 |
| wpwrak | kristianpaul: you mean for "world domination, FAST" ? | 14:37 |
| lekernel | kyak, yeah, and we should replace that | 14:48 |
| lekernel | s/matlab/scipy | 14:48 |
| lekernel | s/hdlcoder/migen | 14:48 |
| kyak | lekernel: what are your thoughts about replacing Simulink? | 14:57 |
| kyak | i mean, even System Generator from Xilinx uses it as a base | 14:57 |
| lekernel | same. everything mathworks should die and be replaced with python and migen. | 14:58 |
| lekernel | the problem with replacing simulink is all open source UI toolkits are massive piles of turd | 14:58 |
| kyak | that's pretty ambitious | 14:58 |
| lekernel | maybe e17 libraries are better, still need to look at them | 14:58 |
| kyak | simulink is not just an MATLAB ui | 14:59 |
| kyak | it's much more | 14:59 |
| lekernel | I know, but the annoying part will be the UI | 14:59 |
| lekernel | that's what people want, too | 14:59 |
| kyak | that's correct | 15:00 |
| kyak | just wondering why did you even mention LabView? | 15:00 |
| kyak | if everything mathworks should die, everything ni should die, too? | 15:01 |
| lekernel | maybe :) I'm actually less familiar with LabView | 15:02 |
| lekernel | but it just the first example that come to my mind when writing that slide :) | 15:02 |
| kyak | well, anyway, it's awesome. I know the amount of work MathWorks put into their HDL Coder, so it's amazing what you did (all alone or with just few people) | 15:03 |
| lekernel | well, I think Pytholite still lacks many features that HDL Coder has | 15:04 |
| lekernel | but someday we'll get there, hopefully | 15:05 |
| kristianpaul | wpwrak: yeap ;) | 15:36 |
| florent_ | Hi everyone | 16:22 |
| florent_ | I'm playing a bit with the Milkymist stuff and especially Migen ans wanted to discuss with you | 16:22 |
| florent_ | *and | 16:22 |
| florent_ | we already echanged a little on the dev-list about embedded blocks or milkymist-migen-port | 16:23 |
| florent_ | but unfortunately I didn't had time at the end of the year to continue working on that | 16:24 |
| florent_ | time I have now ;) | 16:24 |
| lekernel | hi florent_ | 16:25 |
| florent_ | hi! | 16:25 |
| florent_ | I have some technical question | 16:26 |
| florent_ | but before I just want to give you a little feedback of Migen | 16:26 |
| florent_ | I've tried Migen on a to code a small logic analyzer, it was difficult to start using it but after it was very frustrating to get back to vhdl | 16:27 |
| florent_ | I'm planning to use it on some projects but I don't think my customers are ready to switch to it;;; | 16:28 |
| florent_ | ... | 16:28 |
| florent_ | To learn and also to try to convince my customers I've planned some project using it | 16:29 |
| florent_ | maybe someone here will be interested? | 16:30 |
| florent_ | -The first one is a small port of Milkymist-ng to a De0Nano using Lm32/Asmicon/Uart/Gpios/etc... | 16:31 |
| florent_ | -The second one is a port of Milkymist-ng to a KC705 | 16:31 |
| florent_ | for the first project I want to use Asmicon | 16:33 |
| florent_ | I've started to implement if | 16:33 |
| florent_ | *it | 16:33 |
| florent_ | but the Sdram on the De0Nano is only 16 bits wide | 16:34 |
| florent_ | and Asmicon is doing some assertions with the d_with | 16:34 |
| florent_ | the first one is in the multiplexer | 16:34 |
| florent_ | and the others one is in Wishbone2Asmi | 16:35 |
| florent_ | Have you more informations about the width limitations in the Asmicon? | 16:37 |
| florent_ | I understand the d_width limitation on the wishbone2Asmi module but not the limitation in the controller | 16:38 |
| lekernel | the only assert I see in asmicon multiplexer is https://github.com/milkymist/milkymist-ng/blob/master/milkymist/asmicon/multiplexer.py#L160 | 16:39 |
| lekernel | it's not d_width, it's the frequency ratio between SoC and DRAM | 16:40 |
| florent_ | Ah ok | 16:42 |
| florent_ | It's was another limitation | 16:42 |
| florent_ | in fact I'm using a Sdram, so I have only 1 phase | 16:42 |
| lekernel | what's the SDRAM? PC133? | 16:42 |
| florent_ | do you think I will have so trouble with the multiplexer in this configuration? | 16:43 |
| lekernel | well you can run SDRAM at 133MHz and SoC at 67... then you have 2 phases | 16:43 |
| florent_ | If I remove the assertion | 16:43 |
| lekernel | but if everything can meet timing at 133MHz or maybe even 100MHz it could be better | 16:43 |
| lekernel | with 1 phase | 16:43 |
| lekernel | well you have to add 1-phase support to the multiplexer :) I have not coded it | 16:44 |
| florent_ | Ok, no problem, that just what I wanted to know about that | 16:44 |
| lekernel | what's the maximum frequency of your SDRAM part? | 16:44 |
| lekernel | if you run a 1:2 frequency ratio system then you have 32-bit data | 16:45 |
| lekernel | would help with wishbone | 16:45 |
| lekernel | there are some SDRAM parts that can do 166MHz | 16:45 |
| florent_ | Let me check the DDR on the De0Nano | 16:46 |
| lekernel | it's not DDR | 16:46 |
| florent_ | yes sorry | 16:46 |
| florent_ | the max frequency is 143MHz | 16:46 |
| lekernel | ok. and what's the maximum frequency of lm32 in that fpga? | 16:47 |
| florent_ | more than 100Mhz iirc | 16:47 |
| lekernel | ah. so I guess you don't want to limit it to 143/2=71.5MHz ... | 16:48 |
| florent_ | In fact it's not so important | 16:48 |
| florent_ | I'm making the De0Nano to: | 16:49 |
| lekernel | you can run with 1 phase and BL=1 (ie no bursting) | 16:49 |
| florent_ | - learn more about Migen and the Asmicon | 16:49 |
| lekernel | and 16-bit data (then you need to adapt the wishbone) | 16:49 |
| florent_ | - to prepare the KC705 port | 16:49 |
| lekernel | ASMI is really designed for new SDRAM :) | 16:50 |
| florent_ | I think I will run at 1:2 frequency for a first attempt | 16:50 |
| lekernel | hmm, pick your poison | 16:50 |
| lekernel | if you use a frequency ratio system, you need to mess with the DDR registers | 16:50 |
| lekernel | if you don't, you can use simple I/O flip-flops, and you need to adapt multiplexer and wishbone bridge | 16:51 |
| florent_ | I will have to check witch adaptation is the easier ;) | 16:51 |
| lekernel | it's also hard to tell which one would make the faster system | 16:52 |
| florent_ | In fact I don't care about perfomance on the De0Nano | 16:53 |
| lekernel | modern DRAMs happily run at 800+MHz, so they're rarely the limiting factor with those frustratingly slow FPGAs | 16:53 |
| florent_ | it's only that I don't work to start using ASMICON with the kintex7... | 16:53 |
| florent_ | *want | 16:54 |
| lekernel | ah, I have some ideas for the kintex7 :) | 16:54 |
| florent_ | ah? | 16:54 |
| lekernel | yeah | 16:54 |
| lekernel | you need to use DQS | 16:54 |
| lekernel | for reading | 16:54 |
| lekernel | the current trick with ISERDES won't work, DDR3 timing figures are just too tight | 16:55 |
| florent_ | that's why they introduced IN_FIFO and OUT_FIFO I think | 16:55 |
| lekernel | so we won't use the ISERDES - just IDDR2 | 16:55 |
| lekernel | put the data into a FIFO | 16:56 |
| lekernel | (a soft FIFO) | 16:56 |
| florent_ | In a first time I was planning to use the Xilinx Phy on the KC705 | 16:56 |
| lekernel | and read the data assuming the worst case (late) DQS arrival | 16:56 |
| florent_ | since it's a SODIMM , I have to do read and write leveling | 16:57 |
| lekernel | now there's a catch - as you know DQS stops when there is no more data to transfer, so there will be some data stuck in the registers | 16:57 |
| lekernel | the idea is to make the controller insert a dummy data read (just repeat the last read command, which will always be a page hit) to make the DDR3 wiggle its DQS pins | 16:58 |
| lekernel | every time there is a "bubble" in the flow of read requests | 16:58 |
| lekernel | I would advise against using IN_FIFO and OUT_FIFO, they're very badly documented | 16:59 |
| lekernel | and quite a big mess... | 16:59 |
| lekernel | I think the "dummy read" solution + IDDR + soft FIFO is simpler and more elegant | 16:59 |
| florent_ | I totally agree with you but using the Xilinx phy can be a first step | 17:01 |
| florent_ | ASMICON+ Xilinx Phy | 17:01 |
| lekernel | I think you'll spend more time debugging it than implementing the soft-FIFO solution :) | 17:01 |
| florent_ | and after ASMICON + custom phy | 17:01 |
| lekernel | oh and btw - some PHYs have unpredictable read latency | 17:02 |
| florent_ | and I'm used to the Xilinx Phy | 17:02 |
| lekernel | which adds to the mess of DRAM scheduling, and the ASMICON design doesn't support it | 17:02 |
| florent_ | hmm yes | 17:02 |
| lekernel | my solution has a fixed read latency | 17:02 |
| florent_ | that's was another question I have about ASMICON | 17:03 |
| florent_ | I see read_time and write_time parameters, does the ASMICON needs to be aware of phy latency? | 17:04 |
| lekernel | yes, of course | 17:04 |
| florent_ | Ok so I first have to check if Xilinx Phy latency is predictable... | 17:06 |
| lekernel | do you have a URL to that Xilinx PHY? last time I checked they didn't publish it | 17:06 |
| lekernel | is it that horrendous design generated by a horrible java application? | 17:06 |
| florent_ | yes it's the MIG | 17:06 |
| lekernel | last time I ran it you couldn't generate the PHY aline | 17:07 |
| lekernel | alone | 17:07 |
| lekernel | you had to extract it from the generated VHDL mess | 17:07 |
| florent_ | http://www.xilinx.com/products/intellectual-property/MIG.htm | 17:07 |
| lekernel | also: no documentation, RTFS | 17:07 |
| florent_ | In fact the MIG is a full controller : controller + phy | 17:08 |
| lekernel | yes | 17:08 |
| florent_ | I've worked on a project with a custom controller + only the xilinx phy | 17:08 |
| florent_ | There was enough documentation for that | 17:09 |
| florent_ | only lots of parameters to support! | 17:09 |
| florent_ | The phy use IN_FIFO/OUT_FIFO/PHY_CONTROL hard blocks | 17:10 |
| lekernel | yeah I had a look at that source | 17:10 |
| lekernel | for kintex 7 and ddr3 | 17:10 |
| lekernel | and I don't like it | 17:10 |
| florent_ | But those are not documented or supported | 17:10 |
| florent_ | And the Phy used lots of resources | 17:11 |
| lekernel | even with the hard blocks? hm | 17:11 |
| lekernel | yeah I remember there was some large FSMs in there | 17:11 |
| lekernel | haven't tried synthesizing it... | 17:11 |
| lekernel | IDDR + soft-FIFO scores one more point I guess | 17:12 |
| florent_ | In fact the Phy does everythin : DDR configuration / and Read/Write Leveling | 17:12 |
| florent_ | Read and write leveling take at least 1000 Luts each | 17:12 |
| lekernel | read leveling is solved in a more simple way by using DQS as clock and assuming the worst case DQS arrival for data recapture using the system clock | 17:13 |
| florent_ | With support read and write leveling on milkymist it's maybe better to implement a software solution | 17:13 |
| lekernel | write leveling can be solved by having independent DDR3 chips instead of a DIMM | 17:13 |
| florent_ | Ah ok, i didn't understand that | 17:14 |
| lekernel | if you only use one DDR3 chip on the DIMM you can skip write leveling | 17:14 |
| lekernel | or rather implement a much simpler version of it | 17:14 |
| lekernel | also this sort of things should be done by some BIOS running on a softcore CPU, not a FSM anyway | 17:15 |
| florent_ | I've read some time ago that you were planning a M^3 | 17:16 |
| florent_ | is it still planned? | 17:16 |
| lekernel | yeah, but I need a clearer marketing case for it | 17:17 |
| florent_ | Ah Ok | 17:17 |
| florent_ | And wouldn't it be more easier to have a board with all the FPGA/DDR/Flash and another mezzanine with the functionnalites? | 17:19 |
| lekernel | I'll start with a simpler M1-based video mixer, too | 17:19 |
| florent_ | because I would be interested by a such board! | 17:19 |
| lekernel | I don't know. if you want to ship end user products eventually, this adds to the complexity of the assembly process and the mechanical design. | 17:20 |
| lekernel | also M3 would have high speed signals like HDMI, Displayport or Thunderbolt *g* | 17:21 |
| florent_ | yes of course but you can attract all the arduino community with such a board | 17:21 |
| lekernel | no you can't | 17:21 |
| lekernel | I'm watching Lophilo struggle ... | 17:21 |
| florent_ | ?? | 17:22 |
| florent_ | don't know | 17:22 |
| lekernel | http://lophilo.com/ | 17:22 |
| lekernel | http://www.google.com/trends/explore#q=arduino,lophilo | 17:23 |
| lekernel | and I can tell you they're trying hard... | 17:23 |
| florent_ | yes but the problem it's very difficult to learn fpga | 17:24 |
| lekernel | and it's expensive blah blah blah | 17:25 |
| lekernel | bottom line: you can't :) | 17:25 |
| florent_ | don't know... maybe migen can help | 17:25 |
| lekernel | I think Arduino fans are simply the wrong target | 17:26 |
| lekernel | besides, I love technology, and making simple boards bores me. | 17:27 |
| florent_ | yes I can understand | 17:27 |
| florent_ | I have to go | 17:28 |
| florent_ | thanks for the discussion and advices | 17:29 |
| lekernel | bye, thanks for coming bye! | 17:29 |
| lekernel | keep us posted about your DRAM adventures | 17:29 |
| lekernel | and good luck! | 17:29 |
| florent_ | of course, I hope I won't have to ask you too much boring questions ;) | 17:30 |
| florent_ | bye | 17:30 |
| lekernel | questions about DRAM are rarely boring | 17:30 |
| lekernel | and we need good ASMI documentation/knowledge base anyway | 17:31 |
| lekernel | so please ask them on a logged channel or list | 17:31 |
| florent_ | ok I'll do that | 17:31 |
| Fallenou | lekernel: for the workshop, networkx v1.1 is up to date enough ? (package from debian squeeze) | 20:36 |
| lekernel | I think so | 20:36 |
| lekernel | but I don't really know. try running mm soc build.py and see if it screams | 20:37 |
| Fallenou | build.py says "ImportError: No module named netowrkx" | 20:42 |
| Fallenou | oh ok I have the networkx module for python 2.6 not for python3 | 20:43 |
| Fallenou | I used easy_install3 to install networkx 1.7 (as a .egg file) it ave me a bunch of syntax error but now I can import networkx in python3 | 20:51 |
| Fallenou | weird that the install throws so much errors | 20:51 |
| Fallenou | ok good make all works fine | 20:57 |
| Fallenou | mwalle: are you here ? | 21:06 |
| Fallenou | I clonsed your github milkymist repository, checked out the "mmu" branch, then I went to cores/lm32/test and did "make" and then vvp tb_lm32 +prog=qemu_testcases/test_mmu.vh | 21:09 |
| Fallenou | it does not seem to ever $finish | 21:09 |
| Fallenou | am I doing it wrong ? | 21:09 |
| Fallenou | it seems pmem_adr takes values 0, 0001, 0002, 0003 and then 0000 and it stays 0000 | 21:28 |
| Fallenou | pmem_dat_o takes values C3A00000 , 34010000, C3A00000, 34010000, C3A00000 | 21:29 |
| Fallenou | I can't see "pmem" in gtkwave though to check that all program data is OK | 21:29 |
| --- Sat Jan 5 2013 | 00:00 | |
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