#milkymist IRC log for Friday, 2013-01-04

lekernelwpwrak, I have forwarded your email to Adrien13:10
lekernelre. wire characterization13:10
lekernelmwalle, yup13:10
lekernelyou should have come to the conference mwalle :)13:11
wpwraklekernel: ah, thanks !13:28
Fallenoulekernel: ahah nice link, I never go to Quick btw :p13:45
Fallenoueven during the star wars burgers sales ... :p13:45
wpwrakFallenou: they're very efficient in the future. crash a spacecraft ... don't bemoan the dead, have a burgers sale ! kinda like the happy face of soylent green :)13:49
Fallenouwwwwhat ?!13:54
Fallenouplease send me samples of what you take :p13:54
atgreenlekernel: watching your migen talk right now - thanks for posting13:57
wpwrakFallenou: just exploiting the creative phase between waking up and the first dose of caffeine :)13:59
kyaklekernel: just watched your video for Migen, very impressive. Since you mentioned dataflow programming, have you seen HDL Coder? (http://www.mathworks.com/products/hdl-coder/)14:27
wpwrakfrequency 6000000 -> new real frequency 46570.9, delay 0   operating without delay   :)14:28
kyakit has nothing to do with FOSS, of course, but it's a yet another approach from higher level languages to hardware design14:28
wpwrakoops. wrong channel14:29
kyakwpwrak: chaos and confusion!14:29
wpwrakkyak: now you're getting into the spirit :)14:30
kyakwe should team up :)14:31
wpwrakyeah. you take the northern hemisphere, i take the south :)14:32
kristianpaulwpwrak: where is your turbo button? :-)14:33
wpwrakkristianpaul: you mean for "world domination, FAST" ?14:37
lekernelkyak, yeah, and we should replace that14:48
kyaklekernel: what are your thoughts about replacing Simulink?14:57
kyaki mean, even System Generator from Xilinx uses it as a base14:57
lekernelsame. everything mathworks should die and be replaced with python and migen.14:58
lekernelthe problem with replacing simulink is all open source UI toolkits are massive piles of turd14:58
kyakthat's pretty ambitious14:58
lekernelmaybe e17 libraries are better, still need to look at them14:58
kyaksimulink is not just an MATLAB ui14:59
kyakit's much more14:59
lekernelI know, but the annoying part will be the UI14:59
lekernelthat's what people want, too14:59
kyakthat's correct15:00
kyakjust wondering why did you even mention LabView?15:00
kyakif everything mathworks should die, everything ni should die, too?15:01
lekernelmaybe :) I'm actually less familiar with LabView15:02
lekernelbut it just the first example that come to my mind when writing that slide :)15:02
kyakwell, anyway, it's awesome. I know the amount of work MathWorks put into their HDL Coder, so it's amazing what you did (all alone or with just few people)15:03
lekernelwell, I think Pytholite still lacks many features that HDL Coder has15:04
lekernelbut someday we'll get there, hopefully15:05
kristianpaulwpwrak: yeap ;)15:36
florent_Hi everyone16:22
florent_I'm playing a bit with the Milkymist stuff and especially Migen ans wanted to discuss with you16:22
florent_we already echanged a little on the dev-list about embedded blocks or milkymist-migen-port16:23
florent_but unfortunately I didn't had time at the end of the year to continue working on that16:24
florent_time I have now ;)16:24
lekernelhi florent_16:25
florent_I have some technical question16:26
florent_but before I just want to give you a little feedback of Migen16:26
florent_I've tried Migen on a to code a small logic analyzer, it was difficult to start using it but after it was very frustrating to get back to vhdl16:27
florent_I'm planning to use it on some projects but I don't think my customers are ready to switch to it;;;16:28
florent_To learn and also to try to convince my customers I've planned some project using it16:29
florent_maybe someone here will be interested?16:30
florent_-The first one is a small port of Milkymist-ng to a De0Nano using Lm32/Asmicon/Uart/Gpios/etc...16:31
florent_-The second one is a port of Milkymist-ng to a KC70516:31
florent_for the first project I want to use Asmicon16:33
florent_I've started to implement if16:33
florent_but the Sdram on the De0Nano is only 16 bits wide16:34
florent_and Asmicon is doing some assertions with the d_with16:34
florent_the first one is in the multiplexer16:34
florent_and the others one is in Wishbone2Asmi16:35
florent_Have you more informations about the width limitations in the Asmicon?16:37
florent_I understand the d_width limitation on the wishbone2Asmi module but not the limitation in the controller16:38
lekernelthe only assert I see in asmicon multiplexer is https://github.com/milkymist/milkymist-ng/blob/master/milkymist/asmicon/multiplexer.py#L16016:39
lekernelit's not d_width, it's the frequency ratio between SoC and DRAM16:40
florent_Ah ok16:42
florent_It's was another limitation16:42
florent_in fact I'm using a Sdram, so I have only 1 phase16:42
lekernelwhat's the SDRAM? PC133?16:42
florent_do you think I will have so trouble with the multiplexer in this configuration?16:43
lekernelwell you can run SDRAM at 133MHz and SoC at 67... then you have 2 phases16:43
florent_If I remove the assertion16:43
lekernelbut if everything can meet timing at 133MHz or maybe even 100MHz it could be better16:43
lekernelwith 1 phase16:43
lekernelwell you have to add 1-phase support to the multiplexer :) I have not coded it16:44
florent_Ok, no problem, that just what I wanted to know about that16:44
lekernelwhat's the maximum frequency of your SDRAM part?16:44
lekernelif you run a 1:2 frequency ratio system then you have 32-bit data16:45
lekernelwould help with wishbone16:45
lekernelthere are some SDRAM parts that can do 166MHz16:45
florent_Let me check the DDR on the De0Nano16:46
lekernelit's not DDR16:46
florent_yes sorry16:46
florent_the max frequency is 143MHz16:46
lekernelok. and what's the maximum frequency of lm32 in that fpga?16:47
florent_more than 100Mhz iirc16:47
lekernelah. so I guess you don't want to limit it to 143/2=71.5MHz ...16:48
florent_In fact it's not so important16:48
florent_I'm making the De0Nano to:16:49
lekernelyou can run with 1 phase and BL=1 (ie no bursting)16:49
florent_- learn more about Migen and the Asmicon16:49
lekerneland 16-bit data (then you need to adapt the wishbone)16:49
florent_- to prepare the KC705 port16:49
lekernelASMI is really designed for new SDRAM :)16:50
florent_I think I will run at 1:2 frequency for a first attempt16:50
lekernelhmm, pick your poison16:50
lekernelif you use a frequency ratio system, you need to mess with the DDR registers16:50
lekernelif you don't, you can use simple I/O flip-flops, and you need to adapt multiplexer and wishbone bridge16:51
florent_I will have to check witch adaptation is the easier ;)16:51
lekernelit's also hard to tell which one would make the faster system16:52
florent_In fact I don't care about perfomance on the De0Nano16:53
lekernelmodern DRAMs happily run at 800+MHz, so they're rarely the limiting factor with those frustratingly slow FPGAs16:53
florent_it's only that I don't work to start using ASMICON with the kintex7...16:53
lekernelah, I have some ideas for the kintex7 :)16:54
lekernelyou need to use DQS16:54
lekernelfor reading16:54
lekernelthe current trick with ISERDES won't work, DDR3 timing figures are just too tight16:55
florent_that's why they introduced IN_FIFO and OUT_FIFO I think16:55
lekernelso we won't use the ISERDES - just IDDR216:55
lekernelput the data into a FIFO16:56
lekernel(a soft FIFO)16:56
florent_In a first time I was planning to use the Xilinx Phy on the KC70516:56
lekerneland read the data assuming the worst case (late) DQS arrival16:56
florent_since it's a SODIMM , I have to do read and write leveling16:57
lekernelnow there's a catch - as you know DQS stops when there is no more data to transfer, so there will be some data stuck in the registers16:57
lekernelthe idea is to make the controller insert a dummy data read (just repeat the last read command, which will always be a page hit) to make the DDR3 wiggle its DQS pins16:58
lekernelevery time there is a "bubble" in the flow of read requests16:58
lekernelI would advise against using IN_FIFO and OUT_FIFO, they're very badly documented16:59
lekerneland quite a big mess...16:59
lekernelI think the "dummy read" solution + IDDR + soft FIFO is simpler and more elegant16:59
florent_I  totally agree with you but using the Xilinx phy can be a first step17:01
florent_ASMICON+ Xilinx Phy17:01
lekernelI think you'll spend more time debugging it than implementing the soft-FIFO solution :)17:01
florent_and after ASMICON + custom phy17:01
lekerneloh and btw - some PHYs have unpredictable read latency17:02
florent_and I'm used to the Xilinx Phy17:02
lekernelwhich adds to the mess of DRAM scheduling, and the ASMICON design doesn't support it17:02
florent_hmm yes17:02
lekernelmy solution has a fixed read latency17:02
florent_that's was another question I have about ASMICON17:03
florent_I see read_time and write_time parameters, does the ASMICON needs to be aware of phy latency?17:04
lekernelyes, of course17:04
florent_Ok so I first have to check if Xilinx Phy latency is predictable...17:06
lekerneldo you have a URL to that Xilinx PHY? last time I checked they didn't publish it17:06
lekernelis it that horrendous design generated by a horrible java application?17:06
florent_yes it's the MIG17:06
lekernellast time I ran it you couldn't generate the PHY aline17:07
lekernelyou had to extract it from the generated VHDL mess17:07
lekernelalso: no documentation, RTFS17:07
florent_In fact the MIG is a full controller : controller + phy17:08
florent_I've worked on a project with a custom controller + only the xilinx phy17:08
florent_There was enough documentation for that17:09
florent_only lots of parameters to support!17:09
florent_The phy use IN_FIFO/OUT_FIFO/PHY_CONTROL hard blocks17:10
lekernelyeah I had a look at that source17:10
lekernelfor kintex 7 and ddr317:10
lekerneland I don't like it17:10
florent_But those are not documented or supported17:10
florent_And the Phy used lots of resources17:11
lekerneleven with the hard blocks? hm17:11
lekernelyeah I remember there was some large FSMs in there17:11
lekernelhaven't tried synthesizing it...17:11
lekernelIDDR + soft-FIFO scores one more point I guess17:12
florent_In fact the Phy does everythin : DDR configuration / and Read/Write Leveling17:12
florent_Read and write leveling take at least 1000 Luts each17:12
lekernelread leveling is solved in a more simple way by using DQS as clock and assuming the worst case DQS arrival for data recapture using the system clock17:13
florent_With support read and write leveling on milkymist it's maybe better to implement a software solution17:13
lekernelwrite leveling can be solved by having independent DDR3 chips instead of a DIMM17:13
florent_Ah ok, i didn't understand that17:14
lekernelif you only use one DDR3 chip on the DIMM you can skip write leveling17:14
lekernelor rather implement a much simpler version of it17:14
lekernelalso this sort of things should be done by some BIOS running on a  softcore CPU, not a FSM anyway17:15
florent_I've read some  time ago that you were planning a M^317:16
florent_is it still planned?17:16
lekernelyeah, but I need a clearer marketing case for it17:17
florent_Ah Ok17:17
florent_And wouldn't it be more easier to have a board with all the FPGA/DDR/Flash and another mezzanine with the functionnalites?17:19
lekernelI'll start with a simpler M1-based video mixer, too17:19
florent_because I would be interested by a such board!17:19
lekernelI don't know. if you want to ship end user products eventually, this adds to the complexity of the assembly process and the mechanical design.17:20
lekernelalso M3 would have high speed signals like HDMI, Displayport or Thunderbolt *g*17:21
florent_yes of course but you can attract all the arduino community with such a board17:21
lekernelno you can't17:21
lekernelI'm watching Lophilo struggle ...17:21
florent_don't know17:22
lekerneland I can tell you they're trying hard...17:23
florent_yes but the problem it's very difficult to learn fpga17:24
lekerneland it's expensive blah blah blah17:25
lekernelbottom line: you can't :)17:25
florent_don't know... maybe migen can help17:25
lekernelI think Arduino fans are simply the wrong target17:26
lekernelbesides, I love technology, and making simple boards bores me.17:27
florent_yes I can understand17:27
florent_I have to go17:28
florent_thanks for the discussion and advices17:29
lekernelbye, thanks for coming bye!17:29
lekernelkeep us posted about your DRAM adventures17:29
lekerneland good luck!17:29
florent_of course, I hope I won't have to ask you too much boring questions ;)17:30
lekernelquestions about DRAM are rarely boring17:30
lekerneland we need good ASMI documentation/knowledge base anyway17:31
lekernelso please ask them on a logged channel or list17:31
florent_ok I'll do that17:31
Fallenoulekernel: for the workshop, networkx v1.1 is up to date enough ? (package from debian squeeze)20:36
lekernelI think so20:36
lekernelbut I don't really know. try running mm soc build.py and see if it screams20:37
Fallenoubuild.py says "ImportError: No module named netowrkx"20:42
Fallenouoh ok I have the networkx module for python 2.6 not for python320:43
FallenouI used easy_install3 to install networkx 1.7 (as a .egg file) it ave me a bunch of syntax error but now I can import networkx in python320:51
Fallenouweird that the install throws so much errors20:51
Fallenouok good make all works fine20:57
Fallenoumwalle: are you here ?21:06
FallenouI clonsed your github milkymist repository, checked out the "mmu" branch, then I went to cores/lm32/test and did "make" and then vvp tb_lm32 +prog=qemu_testcases/test_mmu.vh21:09
Fallenouit does not seem to ever $finish21:09
Fallenouam I doing it wrong ?21:09
Fallenouit seems pmem_adr takes values 0, 0001, 0002, 0003 and then 0000 and it stays 000021:28
Fallenoupmem_dat_o takes values C3A00000 , 34010000, C3A00000, 34010000, C3A0000021:29
FallenouI can't see "pmem" in gtkwave though to check that all program data is OK21:29
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