#milkymist IRC log for Wednesday, 2012-12-19

GitHub183[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/3fae6c8f03a4...47f5fc70e48b15:10
GitHub183migen/master 9c65402 Sebastien Bourdeauducq: pytholite: prune unused registers15:10
GitHub183migen/master 47f5fc7 Sebastien Bourdeauducq: pytholite: fix bug with constant assignment to register15:10
mwallelarsc: are you there?16:45
larscI'm here16:48
mwallei have a question regarding handle_level_irq, maybe you can help me :)16:48
mwallethe sequence is "irq -> mask_ack -> isr -> unmask" right?16:49
larscyes16:50
mwallebut for level sensitive irqs the mask_ack is only a mask, isn't it? because the isr hasn't reset the device interrupt output, the interrupt is still asserted, and the pending status won't be cleared with an ack16:50
larscsort of16:51
larschandle_level_irq is kind of a misnomer anyway16:51
mwallebecause?16:52
larsci actually made a drawing explaining the difference between handle_level_irq and handle_edge_irq, let me find it16:53
mwallek16:53
mwallei had a look at the lm32 port, where we use the handle_level_irq. i don't know why this is working with level-sensitive interrupts (iirc the minimac2 has level-sensitive ones)16:55
mwalleshouldn't be the sequence "irq -> mask -> isr -> ack & unmask" ?16:56
larschttp://metafoo.de/irq_types.svg16:58
larscthe first should be handled by handle_edge_irq the second by handle_level_irq16:58
larscalthough the second can also be triggered by edge irqs16:59
larscyea, exactly, with the current sequence the interrupts are actually triggered twice17:00
larscactually I got it slightly wrong. So the first one in the picutre is the hardware which works with handle_level_irq and handle_edge_irq for level and edge irqs17:02
larscthe second one works with edge triggered irqs when using handle_level_irq17:03
larscfor a level sensitive irq you acutally need some kind of translation hardware which turns the level irq into a edge irq17:04
larscif you want to use handel_level_irq17:04
larscotherwise you'll see the irq twice17:05
mwalleok makes sense17:05
mwallebtw i had the same thought on the pending and the mask register17:06
mwalle(where the bitwise and is located, before or after the pending register)17:07
mwallebut then, why hadn't we seen some spurious interrupts? (assuming the driver ISR correctly returns IRQ_HANDLED and IRQ_NONE17:09
larscdo we ever return IRQ_NONE?17:10
mwalleno ;)17:10
mwalleok, that explains a lot17:10
mwallelarsc: thanks for the chat :)17:11
mwallemh one more, so the solution is to use handle_simple_irq and use mask/generic_handle_irq/ack/unmask ?17:13
larscI don't know. The pending register is kind of annoying, if the irq lines are really level triggered it makes much more sense to just route them through17:17
larsc(as long as the design is synchronous)17:18
mwallelarsc: for lm32 lekernel__ already eliminated the IP register17:54
larscso we are good?17:57
lkcl_roh, lekernel__ - thank you for the suggestion to contact that guy about the openmoko debug board20:07
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