| GitHub183 | [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/3fae6c8f03a4...47f5fc70e48b | 15:10 |
|---|---|---|
| GitHub183 | migen/master 9c65402 Sebastien Bourdeauducq: pytholite: prune unused registers | 15:10 |
| GitHub183 | migen/master 47f5fc7 Sebastien Bourdeauducq: pytholite: fix bug with constant assignment to register | 15:10 |
| mwalle | larsc: are you there? | 16:45 |
| larsc | I'm here | 16:48 |
| mwalle | i have a question regarding handle_level_irq, maybe you can help me :) | 16:48 |
| mwalle | the sequence is "irq -> mask_ack -> isr -> unmask" right? | 16:49 |
| larsc | yes | 16:50 |
| mwalle | but for level sensitive irqs the mask_ack is only a mask, isn't it? because the isr hasn't reset the device interrupt output, the interrupt is still asserted, and the pending status won't be cleared with an ack | 16:50 |
| larsc | sort of | 16:51 |
| larsc | handle_level_irq is kind of a misnomer anyway | 16:51 |
| mwalle | because? | 16:52 |
| larsc | i actually made a drawing explaining the difference between handle_level_irq and handle_edge_irq, let me find it | 16:53 |
| mwalle | k | 16:53 |
| mwalle | i had a look at the lm32 port, where we use the handle_level_irq. i don't know why this is working with level-sensitive interrupts (iirc the minimac2 has level-sensitive ones) | 16:55 |
| mwalle | shouldn't be the sequence "irq -> mask -> isr -> ack & unmask" ? | 16:56 |
| larsc | http://metafoo.de/irq_types.svg | 16:58 |
| larsc | the first should be handled by handle_edge_irq the second by handle_level_irq | 16:58 |
| larsc | although the second can also be triggered by edge irqs | 16:59 |
| larsc | yea, exactly, with the current sequence the interrupts are actually triggered twice | 17:00 |
| larsc | actually I got it slightly wrong. So the first one in the picutre is the hardware which works with handle_level_irq and handle_edge_irq for level and edge irqs | 17:02 |
| larsc | the second one works with edge triggered irqs when using handle_level_irq | 17:03 |
| larsc | for a level sensitive irq you acutally need some kind of translation hardware which turns the level irq into a edge irq | 17:04 |
| larsc | if you want to use handel_level_irq | 17:04 |
| larsc | otherwise you'll see the irq twice | 17:05 |
| mwalle | ok makes sense | 17:05 |
| mwalle | btw i had the same thought on the pending and the mask register | 17:06 |
| mwalle | (where the bitwise and is located, before or after the pending register) | 17:07 |
| mwalle | but then, why hadn't we seen some spurious interrupts? (assuming the driver ISR correctly returns IRQ_HANDLED and IRQ_NONE | 17:09 |
| larsc | do we ever return IRQ_NONE? | 17:10 |
| mwalle | no ;) | 17:10 |
| mwalle | ok, that explains a lot | 17:10 |
| mwalle | larsc: thanks for the chat :) | 17:11 |
| mwalle | mh one more, so the solution is to use handle_simple_irq and use mask/generic_handle_irq/ack/unmask ? | 17:13 |
| larsc | I don't know. The pending register is kind of annoying, if the irq lines are really level triggered it makes much more sense to just route them through | 17:17 |
| larsc | (as long as the design is synchronous) | 17:18 |
| mwalle | larsc: for lm32 lekernel__ already eliminated the IP register | 17:54 |
| larsc | so we are good? | 17:57 |
| lkcl_ | roh, lekernel__ - thank you for the suggestion to contact that guy about the openmoko debug board | 20:07 |
| --- Thu Dec 20 2012 | 00:00 | |
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