| GitHub55 | [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/JhWw5w | 14:43 |
|---|---|---|
| GitHub55 | milkymist-ng/master c44ff89 Sebastien Bourdeauducq: Move Token | 14:43 |
| GitHub55 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6f992415852ef8d4d2c10a597b51b2ad72c43723 | 14:44 |
| GitHub55 | migen/master 6f99241 Sebastien Bourdeauducq: Move Token to migen.flow.transactions | 14:44 |
| GitHub196 | [qemu] mwalle pushed 2 new commits to master: https://github.com/mwalle/qemu/compare/34bff8ff828a...611029910906 | 16:18 |
| GitHub196 | qemu/master be96123 Michael Walle: tests: tcg: lm32: add more test cases... | 16:18 |
| GitHub196 | qemu/master 6110299 Michael Walle: target-lm32: fix cmpgui and cmpgeui opcodes... | 16:18 |
| lekernel__ | Fallenou: what software have you used to create this picture? http://sionneau.net/images/stories/hardware_block_without_pipeline_without_control_transparent.png | 16:36 |
| lekernel__ | http://sionneau.net/images/stories/hardware_block_pipelined_transparent.png | 16:37 |
| lekernel__ | looks much better than what networkx/matplotlib gives | 16:37 |
| Action: Fallenou coughs | 16:41 | |
| Fallenou | M$ Word 2010 | 16:41 |
| Fallenou | sorry | 16:41 |
| Fallenou | with hand placed arrows and squares | 16:42 |
| mwalle | lekernel__: never used shiny ms products? :) | 16:43 |
| lekernel__ | the most recent windows I have used is XP | 16:44 |
| mwalle | lekernel__: btw the lm32_cpu can store the register in blockram which uses a clock shifted by 180deg. that way you can save some registers | 16:46 |
| mwalle | do you think that is also possible on spartan-6? | 16:47 |
| lekernel__ | the register file? | 16:47 |
| mwalle | yeah | 16:47 |
| lekernel__ | isn't it already in block ram? | 16:47 |
| lekernel__ | if you disable the reset | 16:47 |
| lekernel__ | and this doesn't need a shifted clock | 16:47 |
| mwalle | there are two options, CFG_EBR_POSEDGE_REGISTER_FILE and CFG_EBR_NEGEDGE_REGISTER_FILE | 16:48 |
| mwalle | we use the first atm | 16:48 |
| mwalle | the first need some additional buffers | 16:49 |
| lekernel__ | what buffers? | 16:49 |
| lekernel__ | let me check the source ... | 16:52 |
| mwalle | buffers in terms of data buffers, some registers to store intermediate data | 16:52 |
| lekernel__ | you mean it adds a pipeline stage? | 16:52 |
| mwalle | no | 16:53 |
| mwalle | it seems to stall the cpu if there is a read and write at the same time | 16:53 |
| lekernel__ | ah, I think I understand | 16:54 |
| lekernel__ | since it's a dual port RAM, there is a conflict if you read two operands and write one? | 16:54 |
| lekernel__ | (you'd rather need 3 ports) | 16:55 |
| mwalle | they use two rams for the 3 ports | 16:55 |
| lekernel__ | yeah, right :) otherwise performance would suck | 16:55 |
| mwalle | and writes go to both | 16:56 |
| mwalle | "One limitation of the on-chip block RAMs is that one cannot perform a read and write to same location in a cycle (if this is done, then the data read out is indeterminate)" | 16:56 |
| lekernel__ | I'm not sure xilinx has this limitation... in either case, how does clocking the RAM with the opposite clock edge resolves the problem? | 16:59 |
| mwalle | ah, | 16:59 |
| lekernel__ | you do writes with one edge and reads with the other? | 16:59 |
| mwalle | write clock is clk_n | 16:59 |
| mwalle | err | 16:59 |
| mwalle | read clock is clk_n and write clock is clk | 16:59 |
| mwalle | actuall the define has a bad name.. | 17:00 |
| lekernel__ | I would guess either the xilinx silicon doesn't have this limitation, or Xst inserts appropriate conflict detection logic automatically (in which case the corresponding code in lm32_cpu.v serves the only purpose of increasing SLOC) | 17:00 |
| lekernel__ | and I think this is the right thing to do btw | 17:01 |
| mwalle | "this" ? | 17:01 |
| lekernel__ | not having the limitation in silicon, or letting the synthesizer take care of it to match the behavioral code | 17:02 |
| mwalle | ah :) | 17:02 |
| mwalle | well they used the ram slice directly.. so.. ;) | 17:02 |
| lekernel__ | that's also not a good thing to do :) | 17:03 |
| lekernel__ | and this negative clock is very much a hack... should be removed completely imo | 17:05 |
| lekernel__ | I think the overhead of the conflict detection logic is too small to justify it | 17:05 |
| lekernel__ | also, block RAMs sometimes have large setup or clock-to-output times... need to be careful when messing with clocks, otherwise you can end up with a slow design | 17:10 |
| lekernel__ | for example, clocking reads on the negative edge to do asynchronous reads (which aren't supported by silicon) is a sure way to have lousy performance | 17:16 |
| mwalle | lekernel__: according to ug383 there are two clock inputs | 17:20 |
| mwalle | i'm not saying that is good design ;) | 17:20 |
| GitHub72 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/02f8d5c5cbad565cd59a2c73bde7d59561912399 | 18:04 |
| GitHub72 | migen/master 02f8d5c Sebastien Bourdeauducq: Token: support idle_wait | 18:04 |
| GitHub71 | [migen] sbourdeauducq force-pushed master from 02f8d5c to a67f483: https://github.com/milkymist/migen/commits/master | 18:05 |
| GitHub71 | migen/master a67f483 Sebastien Bourdeauducq: Token: support idle_wait | 18:05 |
| GitHub3 | [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/a67f483f0fcd...b06fbdedd6bb | 22:45 |
| GitHub3 | migen/master 1f350ad Sebastien Bourdeauducq: actorlib/sim/SimActor: do not drive busy low when generator yields None | 22:45 |
| GitHub3 | migen/master b06fbde Sebastien Bourdeauducq: fhdl/tools: bitreverse | 22:45 |
| --- Sat Dec 15 2012 | 00:00 | |
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