#milkymist IRC log for Friday, 2012-12-14

GitHub55[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/JhWw5w14:43
GitHub55milkymist-ng/master c44ff89 Sebastien Bourdeauducq: Move Token14:43
GitHub55[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6f992415852ef8d4d2c10a597b51b2ad72c4372314:44
GitHub55migen/master 6f99241 Sebastien Bourdeauducq: Move Token to migen.flow.transactions14:44
GitHub196[qemu] mwalle pushed 2 new commits to master: https://github.com/mwalle/qemu/compare/34bff8ff828a...61102991090616:18
GitHub196qemu/master be96123 Michael Walle: tests: tcg: lm32: add more test cases...16:18
GitHub196qemu/master 6110299 Michael Walle: target-lm32: fix cmpgui and cmpgeui opcodes...16:18
lekernel__Fallenou: what software have you used to create this picture? http://sionneau.net/images/stories/hardware_block_without_pipeline_without_control_transparent.png16:36
lekernel__looks much better than what networkx/matplotlib gives16:37
Action: Fallenou coughs16:41
FallenouM$ Word 201016:41
Fallenouwith hand placed arrows and squares16:42
mwallelekernel__: never used shiny ms products? :)16:43
lekernel__the most recent windows I have used is XP16:44
mwallelekernel__: btw the lm32_cpu can store the register in blockram which uses a clock shifted by 180deg. that way you can save some registers16:46
mwalledo you think that is also possible on spartan-6?16:47
lekernel__the register file?16:47
lekernel__isn't it already in block ram?16:47
lekernel__if you disable the reset16:47
lekernel__and this doesn't need a shifted clock16:47
mwallewe use the first atm16:48
mwallethe first need some additional buffers16:49
lekernel__what buffers?16:49
lekernel__let me check the source ...16:52
mwallebuffers in terms of data buffers, some registers to store intermediate data16:52
lekernel__you mean it adds a pipeline stage?16:52
mwalleit seems to stall the cpu if there is a read and write at the same time16:53
lekernel__ah, I think I understand16:54
lekernel__since it's a dual port RAM, there is a conflict if you read two operands and write one?16:54
lekernel__(you'd rather need 3 ports)16:55
mwallethey use two rams for the 3 ports16:55
lekernel__yeah, right :) otherwise performance would suck16:55
mwalleand writes go to both16:56
mwalle"One limitation of the on-chip block RAMs is that one cannot perform a read and write to same location in a cycle (if this is done, then the data read out is indeterminate)"16:56
lekernel__I'm not sure xilinx has this limitation... in either case, how does clocking the RAM with the opposite clock edge resolves the problem?16:59
lekernel__you do writes with one edge and reads with the other?16:59
mwallewrite clock is clk_n16:59
mwalleread clock is clk_n and write clock is clk16:59
mwalleactuall the define has a bad name..17:00
lekernel__I would guess either the xilinx silicon doesn't have this limitation, or Xst inserts appropriate conflict detection logic automatically (in which case the corresponding code in lm32_cpu.v serves the only purpose of increasing SLOC)17:00
lekernel__and I think this is the right thing to do btw17:01
mwalle"this" ?17:01
lekernel__not having the limitation in silicon, or letting the synthesizer take care of it to match the behavioral code17:02
mwalleah :)17:02
mwallewell they used the ram slice directly.. so.. ;)17:02
lekernel__that's also not a good thing to do :)17:03
lekernel__and this negative clock is very much a hack... should be removed completely imo17:05
lekernel__I think the overhead of the conflict detection logic is too small to justify it17:05
lekernel__also, block RAMs sometimes have large setup or clock-to-output times... need to be careful when messing with clocks, otherwise you can end up with a slow design17:10
lekernel__for example, clocking reads on the negative edge to do asynchronous reads (which aren't supported by silicon) is a sure way to have lousy performance17:16
mwallelekernel__: according to ug383 there are two clock inputs17:20
mwallei'm not saying that is good design ;)17:20
GitHub72[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/02f8d5c5cbad565cd59a2c73bde7d5956191239918:04
GitHub72migen/master 02f8d5c Sebastien Bourdeauducq: Token: support idle_wait18:04
GitHub71[migen] sbourdeauducq force-pushed master from 02f8d5c to a67f483: https://github.com/milkymist/migen/commits/master18:05
GitHub71migen/master a67f483 Sebastien Bourdeauducq: Token: support idle_wait18:05
GitHub3[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/a67f483f0fcd...b06fbdedd6bb22:45
GitHub3migen/master 1f350ad Sebastien Bourdeauducq: actorlib/sim/SimActor: do not drive busy low when generator yields None22:45
GitHub3migen/master b06fbde Sebastien Bourdeauducq: fhdl/tools: bitreverse22:45
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