#milkymist IRC log for Friday, 2012-11-23

Fallenoumwalle: indeed the address of the instruction changes how it behaves because the cache refill is not at the same moment08:36
Fallenouah nice (resizing icache line to 1024 bytes) :)08:41
Fallenouyou should get rid of any side effect like that08:41
Fallenouwhat I did for my tests was to put 0/1/2/3 nops before my instruction sequence08:45
Fallenouto move the cache refill at different places08:45
GitHub153[migen] sbourdeauducq pushed 5 new commits to master: https://github.com/milkymist/migen/compare/89643bc4346d...20d87682adf112:00
GitHub153migen/master 51e2e6e Sebastien Bourdeauducq: fhdl/verilog: remove empty cases12:00
GitHub153migen/master f098c5c Sebastien Bourdeauducq: pytholite/compiler: pass keyword arguments to gen_io12:00
GitHub153migen/master 0b24a2f Sebastien Bourdeauducq: pytholite/io: support Wishbone writes12:00
GitHub30[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/0b7dd7bdce9606c90c78f8791e5d0fb051b560cb12:30
GitHub30migen/master 0b7dd7b Sebastien Bourdeauducq: pytholite/io: fix Wishbone writes + support sel attribute12:30
GitHub72[migen] sbourdeauducq pushed 5 new commits to master: https://github.com/milkymist/migen/compare/0b7dd7bdce96...9d3e2188630217:27
GitHub72migen/master ab31b4d Sebastien Bourdeauducq: bus: memory initiator17:27
GitHub72migen/master f3efd74 Sebastien Bourdeauducq: uio: support memories17:27
GitHub72migen/master 7c6ebcf Sebastien Bourdeauducq: examples/pytholite/uio: demonstrate memories17:27
GitHub186[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/9d3e21886302...784a3994312518:07
GitHub186migen/master 0f6215a Sebastien Bourdeauducq: fhdl/structure: add Memory.get_port API18:07
GitHub186migen/master 784a399 Sebastien Bourdeauducq: examples/memory: use new get_port API18:07
antgreenjust curious: does JTAG specify a throughput (baud?) rate for communication?  I've never used a JTAG debugger.18:19
wpwraknot sure if there are any "standard" rates. you may just have to go by the data sheets, pick the speed supported by the slowest device in the JTAG chain. if the data sheet doesn't specify a clock, use trial and error.19:18
GitHub50[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/784a39943125...95122bb7782d19:25
GitHub50migen/master f42683b Sebastien Bourdeauducq: fhdl/structure/Memory: fix we width19:25
GitHub50migen/master 95122bb Sebastien Bourdeauducq: pytholite/io: support memory19:25
GitHub138[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/74721b206f4ce4f145916c3e2c47beb7cc12190320:09
GitHub138migen/master 74721b2 Sebastien Bourdeauducq: pytholite: fix import of _Slice20:09
GitHub32[migen] sbourdeauducq pushed 3 new commits to master: https://github.com/milkymist/migen/compare/74721b206f4c...dac0d11e526822:49
GitHub32migen/master d2c61e6 Sebastien Bourdeauducq: sim/generic/multiread: do not return spurious items22:49
GitHub32migen/master 27d87c9 Sebastien Bourdeauducq: fhdl/structure: disable we_granularity when larger than width22:49
GitHub32migen/master dac0d11 Sebastien Bourdeauducq: actorlib/sim: Dumper22:49
--- Sat Nov 24 201200:00

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