#milkymist IRC log for Tuesday, 2012-11-20

wpwrakseems tricky :(00:06
lekernelsecond option is best, CPU is slow enough already12:38
Action: Fallenou does not like the idea of losing cycles12:56
Fallenousorry if I don't answer quickly on proposals I have tons of things to do these days :/12:57
mwallelekernel: yeah and its the hardest to implement ;)19:04
mwalletherefore i'll give the first method a try, first19:05
Fallenoumwalle: are you sure the way it's implemented right now (+ a few fixes maybe) is really not the good way of doing it ?22:31
mwalleFallenou: almost sure, it is possible that the exception in m is not raised22:37
mwallethat is if the pipe from X back is stalled22:37
mwalle(eg an interrupt)22:37
Fallenouhum I'm pretty sure I will raise an exception if there is a dtlb miss in M stage22:41
FallenouSince I keep exception_x asserted until I am certain exception_m will be assterted as well22:42
mwalleyeah but not the instruction in M will raise it22:42
mwallebut the one in X22:42
Fallenouthe question is, will the exception be raised at the correct time22:42
mwalleand since has already reached M, it may be possible, that it passes through the pipe, although there was a miss22:43
Fallenouyou mean, the instruction causing the dtlb miss will then be in W stage ?22:43
mwalleno in M22:43
mwallebut exceptions happen in X22:43
mwalleso if stall_x is TRUE when the load which misses, is in M, no exception occurs22:44
mwallebut the load/store is executed because only A/F/D/X are stalled22:45
mwallemoving the exception handling to the M stage isnt possible, because an exception is treated like a branch, which is already resolved in X22:46
Fallenou23:45 < mwalle> so if stall_x is TRUE when the load which misses, is in M, no exception occurs < but it will happen some timer later22:46
mwalleFallenou: but the load/store is already executed22:47
Action: Fallenou checking the code22:47
mwallethat is, there was a miss, but the store writes to memory anyway22:47
mwallethe whole data bus error is a messed hack22:48
mwallebasically you could just shutdown and enable a red light in case of a data bus error :)22:48
Fallenounothing will be written in the dcache22:49
mwalleD_ERR_I not data bus error22:49
Fallenoubecause way_match will be false22:49
Fallenouand then the write enable will be false as well22:49
Action: Fallenou checking if something could be written back directly to main memory22:51
mwallewhich write enable?22:51
mwalledcache could possibly be disabled and cache is write through22:52
Fallenouin depends on way_match being true22:52
Fallenouand way_match depends on dtlb not missing22:52
Fallenoubut yes I don't prevent the write through from writting to main memory22:53
Fallenouthat's a problem22:53
Fallenougoing to sleep, sorry I don't have that much time for mmu stuff these days :(22:54
mwallemh either i have not the up2date code, or accidentally removed that22:54
mwallebut nonetheless i dont think we should go down that road and pass back the exception from M to X, eg. pretend the instruction in X causing the exception22:56
Fallenouhum ok :/23:00
--- Wed Nov 21 201200:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!