wpwrak | seems tricky :( | 00:06 |
---|---|---|
lekernel | second option is best, CPU is slow enough already | 12:38 |
Action: Fallenou does not like the idea of losing cycles | 12:56 | |
Fallenou | sorry if I don't answer quickly on proposals I have tons of things to do these days :/ | 12:57 |
mwalle | lekernel: yeah and its the hardest to implement ;) | 19:04 |
mwalle | therefore i'll give the first method a try, first | 19:05 |
Fallenou | mwalle: are you sure the way it's implemented right now (+ a few fixes maybe) is really not the good way of doing it ? | 22:31 |
mwalle | Fallenou: almost sure, it is possible that the exception in m is not raised | 22:37 |
mwalle | that is if the pipe from X back is stalled | 22:37 |
mwalle | (eg an interrupt) | 22:37 |
Fallenou | hum I'm pretty sure I will raise an exception if there is a dtlb miss in M stage | 22:41 |
Fallenou | Since I keep exception_x asserted until I am certain exception_m will be assterted as well | 22:42 |
mwalle | yeah but not the instruction in M will raise it | 22:42 |
mwalle | but the one in X | 22:42 |
Fallenou | the question is, will the exception be raised at the correct time | 22:42 |
mwalle | and since has already reached M, it may be possible, that it passes through the pipe, although there was a miss | 22:43 |
Fallenou | you mean, the instruction causing the dtlb miss will then be in W stage ? | 22:43 |
mwalle | no in M | 22:43 |
mwalle | but exceptions happen in X | 22:43 |
Fallenou | yes | 22:43 |
mwalle | so if stall_x is TRUE when the load which misses, is in M, no exception occurs | 22:44 |
mwalle | but the load/store is executed because only A/F/D/X are stalled | 22:45 |
mwalle | moving the exception handling to the M stage isnt possible, because an exception is treated like a branch, which is already resolved in X | 22:46 |
Fallenou | 23:45 < mwalle> so if stall_x is TRUE when the load which misses, is in M, no exception occurs < but it will happen some timer later | 22:46 |
mwalle | Fallenou: but the load/store is already executed | 22:47 |
Action: Fallenou checking the code | 22:47 | |
mwalle | that is, there was a miss, but the store writes to memory anyway | 22:47 |
mwalle | the whole data bus error is a messed hack | 22:48 |
mwalle | basically you could just shutdown and enable a red light in case of a data bus error :) | 22:48 |
Fallenou | nothing will be written in the dcache | 22:49 |
mwalle | D_ERR_I not data bus error | 22:49 |
Fallenou | because way_match will be false | 22:49 |
Fallenou | and then the write enable will be false as well | 22:49 |
Action: Fallenou checking if something could be written back directly to main memory | 22:51 | |
mwalle | which write enable? | 22:51 |
mwalle | dcache could possibly be disabled and cache is write through | 22:52 |
Fallenou | way_dmem_we | 22:52 |
Fallenou | in depends on way_match being true | 22:52 |
Fallenou | and way_match depends on dtlb not missing | 22:52 |
Fallenou | but yes I don't prevent the write through from writting to main memory | 22:53 |
Fallenou | that's a problem | 22:53 |
Fallenou | going to sleep, sorry I don't have that much time for mmu stuff these days :( | 22:54 |
mwalle | mh either i have not the up2date code, or accidentally removed that | 22:54 |
mwalle | but nonetheless i dont think we should go down that road and pass back the exception from M to X, eg. pretend the instruction in X causing the exception | 22:56 |
Fallenou | hum ok :/ | 23:00 |
Fallenou | gn8! | 23:00 |
mwalle | gn8 | 23:01 |
--- Wed Nov 21 2012 | 00:00 |
Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!