| Fallenou | 21:49 < mwalle> Fallenou: if a dtlb miss happens, whats in EA? < it's the address of the instruction causing the miss | 08:49 |
|---|---|---|
| Fallenou | well, not exactly, let me explain | 08:50 |
| Fallenou | exception happen when instruction is in M stage | 08:50 |
| Fallenou | so at first PC_X gets saved into EA | 08:50 |
| Fallenou | but one of the first instruction of the exception vector is to substract 4 from EA | 08:51 |
| Fallenou | so EA ends up with "PC_M" | 08:51 |
| Fallenou | which is the address of the instruction really causing the miss | 08:52 |
| Fallenou | there it is | 08:52 |
| larsc | so it is pc+4 | 08:56 |
| Fallenou | yes | 08:58 |
| Fallenou | I find it clearer to say "the address of instruction causing the miss" | 08:59 |
| Fallenou | well, it depends if you are before or after the substraction | 08:59 |
| larsc | before | 09:02 |
| larsc | obviously ;) | 09:02 |
| larsc | I think what mwalle meant is what's put into EA by the processor when a tlb miss happens | 09:02 |
| Fallenou | oh ok, then yes it's not the instruction causing the miss, it's the next one, the one in X during the miss | 09:56 |
| Fallenou | sorry for the confusion :) | 09:56 |
| Fallenou | who is working at ANSSI here ? | 14:06 |
| Action: Fallenou does not remember | 14:06 | |
| larsc | is that the french NSA? | 20:37 |
| lekernel | somehow... and they're recruiting like crazy atm | 20:50 |
| Fallenou | they want to hire something like 200 more persons in the next year ? | 21:04 |
| mwalle | ah finally, i get the PAE to create a change request to support $clog2 in localparam, too | 21:25 |
| Fallenou | PAE == ? | 21:31 |
| Fallenou | personnal account engineer ? | 21:31 |
| mwalle | application engineer | 21:36 |
| mwalle | product .. | 21:36 |
| Action: larsc just had dinner with some xilinx guys | 21:37 | |
| Fallenou | oh, nice :) | 21:40 |
| Fallenou | is there somewhere a project about USB analyzer using Milkymist SoC or M1 board ? | 21:46 |
| mwalle | larsc: sales guys? | 22:01 |
| wolfspra1l | larsc: anything interesting you learned from the dinner? | 22:04 |
| larsc | mwalle: yes, sales people | 22:18 |
| larsc | wolfspra1l: food is expensive in sweden, tha's all ;) | 22:18 |
| mwalle | larsc: what are you doing in sweden? | 22:18 |
| larsc | I'm going to give a presentation with them tomorrow about jesd204b | 22:18 |
| lekernel | try norway, it's even 50% more expensive than sweden :) | 22:19 |
| mwalle | Fallenou: trying to use the signals in the D stage as read_address input for the tlb ram | 22:21 |
| mwalle | but i guess i wont meet timing | 22:21 |
| Fallenou | ohoh | 22:24 |
| Fallenou | good luck, I never had big timing problems while working on the mmu *lucky* | 22:31 |
| Fallenou | soon I will try to use draw me a pipeline (after a few debugging sessions) to print analyzes of simple pipeline use cases | 22:32 |
| Fallenou | too much things to do ... too few hours in the day ... | 22:32 |
| Fallenou | and a paid job that takes 8 hours per day off my free time | 22:33 |
| Fallenou | real life is hard :p | 22:33 |
| mwalle | All constraints were met. | 22:33 |
| mwalle | mh | 22:33 |
| mwalle | Fallenou: yeah me too ;) | 22:34 |
| Fallenou | 23:34 < mwalle> All constraints were met. < \o/ | 22:34 |
| Fallenou | do you disactivate a lot of cores to speed up synthesis/p&r/etc ? | 22:35 |
| Fallenou | it helps to speed up :) | 22:35 |
| mwalle | yeah | 22:35 |
| Fallenou | but it can show you constraint met when it would not be the case with the full soc :/ | 22:35 |
| mwalle | i know, but i would have bet that even my quick and dirty hack even meet timing | 22:36 |
| Fallenou | I'm calling it a day *tired* | 22:38 |
| Fallenou | gn8! | 22:38 |
| mwalle | gn8 | 22:38 |
| --- Thu Nov 8 2012 | 00:00 | |
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