#milkymist IRC log for Wednesday, 2012-11-07

Fallenou21:49 < mwalle> Fallenou: if a dtlb miss happens, whats in EA? < it's the address of the instruction causing the miss08:49
Fallenouwell, not exactly, let me explain08:50
Fallenouexception happen when instruction is in M stage08:50
Fallenouso at first PC_X gets saved into EA08:50
Fallenoubut one of the first instruction of the exception vector is to substract 4 from EA08:51
Fallenouso EA ends up with "PC_M"08:51
Fallenouwhich is the address of the instruction really causing the miss08:52
Fallenouthere it is08:52
larscso it is pc+408:56
FallenouI find it clearer to say "the address of instruction causing the miss"08:59
Fallenouwell, it depends if you are before or after the substraction08:59
larscobviously ;)09:02
larscI think what mwalle meant is what's put into EA by the processor when a tlb miss happens09:02
Fallenouoh ok, then yes it's not the instruction causing the miss, it's the next one, the one in X during the miss09:56
Fallenousorry for the confusion :)09:56
Fallenouwho is working at ANSSI here ?14:06
Action: Fallenou does not remember14:06
larscis that the french NSA?20:37
lekernelsomehow... and they're recruiting like crazy atm20:50
Fallenouthey want to hire something like 200 more persons in the next year ?21:04
mwalleah finally, i get the PAE to create a change request to support $clog2 in localparam, too21:25
FallenouPAE == ?21:31
Fallenoupersonnal account engineer ?21:31
mwalleapplication engineer21:36
mwalleproduct ..21:36
Action: larsc just had dinner with some xilinx guys21:37
Fallenouoh, nice :)21:40
Fallenouis there somewhere a project about USB analyzer using Milkymist SoC or M1 board ?21:46
mwallelarsc: sales guys?22:01
wolfspra1llarsc: anything interesting you learned from the dinner?22:04
larscmwalle: yes, sales people22:18
larscwolfspra1l: food is expensive in sweden, tha's all ;)22:18
mwallelarsc: what are you doing in sweden?22:18
larscI'm going to give a presentation with them tomorrow about jesd204b22:18
lekerneltry norway, it's even 50% more expensive than sweden :)22:19
mwalleFallenou: trying to use the signals in the D stage as read_address input for the tlb ram22:21
mwallebut i guess i wont meet timing22:21
Fallenougood luck, I never had big timing problems while working on the mmu *lucky*22:31
Fallenousoon I will try to use draw me a pipeline (after a  few debugging sessions) to print analyzes of simple pipeline use cases22:32
Fallenoutoo much things to do ... too few hours in the day ...22:32
Fallenouand a paid job that takes 8 hours per day off my free time22:33
Fallenoureal life is hard :p22:33
mwalleAll constraints were met.22:33
mwalleFallenou: yeah me too ;)22:34
Fallenou23:34 < mwalle> All constraints were met. < \o/22:34
Fallenoudo you disactivate a lot of cores to speed up synthesis/p&r/etc ?22:35
Fallenouit helps to speed up :)22:35
Fallenoubut it can show you constraint met when it would not be the case with the full soc :/22:35
mwallei know, but i would have bet that even my quick and dirty hack even meet timing22:36
FallenouI'm calling it a day *tired*22:38
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