#milkymist IRC log for Sunday, 2012-10-28

wolfspra1lazonenberg: thanks for the floorplans01:17
wolfspra1lnice pictures01:17
wolfspra1lthey make me want to switch to xc7a100 faster :-)01:17
azonenbergwolfspra1l: lol you agree with my assesment that spartan6 is kind of awkward them?01:18
azonenbergoh, and if you thought the lx25 was bad01:19
azonenbergtake a look at the xc6slx75 :P http://i.imgur.com/6AlFb.png01:19
wolfspra1lagree would be too much since I don't have the kind of top-down experience you have01:21
wolfspra1lbut I can definitely imagine that the autorouter will do really bad things in these corners01:21
azonenbergI wasnt talking in terms of toolchain development though01:21
azonenbergAnd yeah01:21
azonenbergThats what i meant01:21
wolfspra1lI think most people vastly overestimate what an autorouter actually does01:22
wolfspra1lI can definitely say that looking at things bottom-up each day :-)01:22
azonenbergI do not, i have a pretty low opinion of their capabilities01:22
azonenbergAll of my PCBs so far have been 100% hand routd01:22
wolfspra1lI talk about the synthesis01:22
wolfspra1lnot board logic01:22
azonenbergand my FPGA designs are normally autorouted by necessity, but usually with manual hints to guide placement01:22
wolfspra1lthe autorouter (synthesis) in the fpga is also, ahem... well01:22
wolfspra1lneeds a lot of guidance :-)01:22
azonenbergSynthesis is source code to unplaced netlist01:23
azonenbergjust so we have terminology strate01:23
wolfspra1lok sorry, of course01:23
wolfspra1lp&r then01:23
azonenbergAnyway, http://i.imgur.com/5uVch.png for example01:23
azonenbergthis is a design i had to manually floorplan01:23
wolfspra1land yes, there are big cutouts in the xc601:23
wolfspra1lin the top and bottom middle, roughly01:23
azonenbergCPU in yellow, rather overcomplicated but functional interconnect in purple, peripherals in blue01:23
wolfspra1land I can imagine that xilinx 'cleans up' things in the xc7, because overall I can say that the xc6 looks like a very clean design after 20+ years on it01:24
azonenbergi had to manually exclude the upper left from routing01:24
wolfspra1lso they must have a habit of cleaning up permanently...01:24
azonenberg7 series also eliminates SLICEXs01:24
wolfspra1l(while the latest and greatest features always destroy those efforts, naturally)01:24
azonenbergif you look closely at most of my designs you will see every other column of CLBs is more heavily loaded01:24
azonenbergbecause my kinds of project tend to use the muxes and adder chains a lot01:24
azonenbergso 7 series will give me much better packing01:24
wolfspra1lxc7 uses b2b (back 2 back) interconnect01:25
azonenbergas in?01:25
azonenbergi've only looked at high level stuff so far01:26
wolfspra1lup to xc6, you alwyas had routing-logic-routing-logic-routing-logic01:26
wolfspra1land in xc7, it's routing-logic-logic-routing-routing-logic-logic-routing01:26
azonenbergSo basically every other column of CLBs is mirrored left to right01:26
wolfspra1lso there are always two routing 'back to back'01:26
azonenbergso you can have easier access to the next column of routing over?01:27
wolfspra1lI don't know the exact innards yet because I haven't read more than a xilinx forum post somewhere01:27
azonenbergI see01:27
wolfspra1lbut yes, some are pointing left some are pointing right01:27
azonenbergI'm only looking so far at the docs and the planahead floorplans01:27
wolfspra1lthey believe maybe this can squeeze out a few more percent in some designs01:27
wolfspra1lbut time will tell (they say themselves)01:27
azonenbergI see01:28
azonenbergWell the floorplans look cleaner than xc6 does01:28
azonenbergand the new CLBs with muxes and adder trees in every column will help01:28
wolfspra1lI have to make a xc6 vs xc7 decision soon01:33
wolfspra1lif I go to xc7, I need to rewrite at least 30% of fpgatools01:34
wolfspra1lthat will be a frustrating 1-2 months01:34
azonenbergmy xc7 dev board if you're interested01:34
wolfspra1lbut then the longer I wait the worse it gets01:34
azonenbergpreliminary design is finished, starting schematic capture in a couple of days01:34
wolfspra1lon the other hand, the more xc6 I implement the better my xc7 rewrite will be01:34
wolfspra1land, finally, every burnt xc7 costs me 140 USD vs. 7 USD for every xc6slx901:35
azonenbergLol yes01:35
azonenbergYou might want to get it nice and stable on xc6 first01:35
wolfspra1lso for the time being I keep hacking on xc6slx9, until I kick myself01:35
wolfspra1lnah, probably not01:35
wolfspra1lthat will take too long01:35
wolfspra1lit's better to speed up, cover as much functionality as possible, to understand the design01:35
wolfspra1lthen use the opportunity of the xc7 rewrite to do a lot of things better01:36
azonenbergalso looking at the xc6slx4 again01:36
azonenbergwow, that is not a lot of CLBs01:36
azonenbergonly five across the whole device01:36
azonenbergand 60 high01:36
wolfspra1lwow that's a big document - SNEAKER01:38
azonenbergOne lot of board fab plus components for a prototype will cost me about $150001:38
azonenberghopefully i can get some of that back by selling blank boards to other people01:38
azonenbergBut i want to be 100% certain i do not need a respin01:38
azonenbergSo i'm trying to leave nothing to chance01:39
azonenbergi'm sure there will be mistakes but i hope they won't be fatal01:40
wolfspra1lwhat's missing in the SNEAKER doc is a high-level intro paragraph about the purpose/goal of the design01:45
azonenbergYeah, it wasnt really written for a general audience01:48
azonenbergit was more for me and the few other people involved with it to discuss requirements01:49
wolfspra1lno matter how small the audience, even 1, I think a few-lines intro is good even for yourself to be able to double-check whether the original goals were met or not01:55
azonenbergYeah, i guess01:55
azonenbergI mean the intention is to be a fairly generic SoC prototyping platform, as well as being something that i can expand my research into since i'm running out of space in the XC6SLX2501:56
azonenbergSo I want more of what I already have, basically01:57
azonenbergplus a few extras like USB and HDMI that i couldn't fit in my last board01:58
wolfspra1lI saw the NOR flash there01:58
azonenbergYeah, I want fast boots and it's a large bitstream01:58
azonenbergso i'm going for BPI rather than SPI01:58
wolfspra1lI think it's fair to say that in milkymist (and before), we learned the hard way that this is not a good long-term solution01:58
azonenbergCan you explain why?01:58
azonenbergYou prefer quad SPI?01:59
azonenbergor regular SPI?01:59
azonenbergor what01:59
wolfspra1ltoo many subtle chip varieties01:59
azonenbergI've specced out a specific component that is on the officially supported list01:59
azonenbergIs your concern that the solution is unstable in general, or that the vendor might stop making that part?01:59
wolfspra1lwith what I've learned, I would only do it if I hard a hard timing requirement that would just rule out the fastest spi02:00
wolfspra1la mix of those02:00
wolfspra1lfew people use nor02:00
wolfspra1llots of hidden bugs will say hello to you over time02:00
azonenbergYou mean parallel NOR02:00
azonenbergbecause SPI flash is NOR too02:00
wolfspra1lI didn't check carefully what you had there02:00
wolfspra1lso maybe what I say is premature02:01
azonenbergI called for 16-bit wide parallel flash from spansion in a 64-BGA02:01
wolfspra1lyour board does not have 'hard' requirements, so in the end it doens't matter much :-)02:02
azonenbergWell, I am hoping for fast boots and quad SPI vs 16-bit parallel is 4x slower02:02
wolfspra1lhard requirements would be a fixed time-to-market, fixed specs (boot time), a certain price point and volume and servicability of the product and users, etc. etc.02:02
azonenbergDoing the math, XC7A200T is 78 Mbits of configuration data02:03
wolfspra1lsince all that doesn't exist, use whatever to boot :-)02:03
wolfspra1lkeep calculating02:03
azonenberglet's say max clock rate of 26 MHz02:03
azonenberg4-bit SPI02:03
wolfspra1lthat's 78mbit uncompressed?02:03
azonenberg104 Mbps02:03
wolfspra1lhow full do you expect your biggest designs to be?02:04
azonenbergSo that would translate to just under a second of boot time02:04
azonenbergThat's for the 200T, initially i'll use the 100 so half that02:04
azonenbergI'm filling half of the XC6SLX25 with one of my design's several major subsystems02:04
azonenbergI'll probably be using a good chunk of the 100T02:04
azonenberg2/3 or so02:04
wolfspra1lif you are in a car or even worse something faster like plane or rocket, and you need to reboot, 10 ms can bring you a long distance forward already (in the air)02:04
wolfspra1lbut I doubt you have that type of requirement02:04
azonenbergNo, but one of the intended applications is in network infrastructure so tens of seconds of downtime on power outage would be an issue02:05
azonenbergone second i can handle02:05
wolfspra1lso whether the booting is 0.5s or 2s, does it matter? (the configuration actually, most likely the whole thing you are building will need longer to be fully functional anyway)02:05
wolfspra1lwell there you go02:05
azonenbergwell, configuration in 500ms is probably doable02:05
wolfspra1lif you have a hard requirement to meet, then that's what you have to do02:05
wolfspra1land that's where parallel nor has its (expensive) niche02:05
azonenbergif i use the 100T02:06
azonenbergWell that will certainly free up a lot of I/O pins02:08
azonenbergi might do that02:08
wolfspra1lunless you want to learn about parallel nor, I think it's better to learn about the new high-speed serial options xilinx has in the 7-series02:13
kristianpaulwolfspra1l: how is the burnt count so far?02:13
wolfspra1lthe quad stuff is new, I think?02:13
wolfspra1lsorry I am speaking just from memory and not double-checking the docs now...02:13
wolfspra1lkristianpaul: no idea, xiangfu is burning I stay on the software side02:14
wolfspra1lthe fpgatools bitstreams themselves have not yet destroyed a single chip, but that's more a sign of how immature it still is02:14
wolfspra1ltoo bad02:14
antgreenhey guys - are there any way to simulate mixed verilog/vhdl code with open source tools?02:19
kristianpaulnot that i remenber to be honest02:20
antgreenhmm too bad.02:21
antgreenI am wrapping a VHDL moxie implementations with a verilog wishbone wrapper, so I guess I'm stuck with vendor tools.02:22
azonenbergwolfspra1l: i have used quad SPI for spartan602:23
azonenbergat up to ~20 MHz so 80 Mbps02:23
azonenbergyou can go a lot faster in 7 series (66 Mhz for artix7)02:24
wolfspra1lI thought there was something new in 702:24
wolfspra1lah ok02:24
azonenbergand up to like 100 in kintex/virtex02:24
azonenbergSo that means an uncompressed artix7 could boot in 155ms lol02:25
azonenbergfor the 100T02:26
azonenbergand that's at 50 MHz, not even the max02:26
azonenbergi'm switching :P02:26
wolfspra1l155ms with what?02:27
wolfspra1lquad spi?02:27
azonenberg50 MHz (max is 66) * 4 bits is 200 Mbps02:28
wolfspra1lso parallel nor becomes an even smaller niche02:28
azonenbergto load ~31 Mbits02:28
wolfspra1lfor the very big devices and hard boot requirements in special gear, you just have to have it02:28
azonenbergso under 150ms if you use the max clock rate02:28
wolfspra1lsay a big kintex02:28
azonenbergwith no compression02:28
wolfspra1lsome have tens of megabytes of config data02:28
azonenbergand yes, for very big devices you dont have much of a choice if you don't want to wait all week02:28
azonenbergIt isn't as bad as you might think02:29
azonenbergthe largest virtex-7 is still only 448 Mbits of data02:29
wolfspra1lif you fly a rocket at mach-6 or more? :-)02:30
azonenbergSo that's just over two seconds on 4-bit parallel02:30
azonenbergor 500ms with 16-bit02:30
azonenbergAnd lol, if you are doing something like that02:30
azonenbergyou configure the fpga before launch02:30
wolfspra1lI think parallel nor has its niche, because it's several times faster - can be02:30
azonenbergor do high-speed partial reconfig02:30
azonenbergYes, it is02:30
wolfspra1lthere's always a need for that somewhere02:30
wolfspra1lbut not in our stuff, typically02:30
azonenbergBut i was hoping for 500ms from power on to operational02:30
azonenbergand it looks like thats doable wit hquad SPI02:31
azonenbergThanks for the suggestion :)02:31
wolfspra1lmaybe you will struggle more with the rest of the ms anyway02:31
azonenberglooks like i can fit another GPIO port02:31
azonenbergand still have some pins free02:31
wpwrak(m1 and nor) there, a large part of the bad experience comes from picking what's pretty much the worse-case type of NOR configuration on the market. all the other configurations are more robust. the other part was of course a flawed reset design. having said that, unless there is hard evidence that a given task needs parallel NOR, i'd go for SPI.02:35
azonenbergGood to know02:35
azonenbergand i didnt realize the 7 series could use so much higher of a clock rate02:35
azonenbergto config i mean02:35
wpwrak(worst-case configuration) specifically about the ability to reliably write-protect critical parts of the NOR. the one we have needs a ridiculously small number of cycles to write or even to remove write protection. with SPI, the much larger number of cycles before anything happens protects you against weird events while power is ramping up/dow and your reset is all wrong. of course, as long as you avoid the latter, there's no worry :)02:44
wpwrakso it's really a combination of a bug (the reset) and an unfortunate sourcing decision (the fragile NOR)02:44
wpwrakwolfspra1l: 6 vs. 7: i think that largely depends on what the goals of your project are. if you're trying to postpone any point where results may be judged by people, then 7 (and then 8, etc.) sounds like a good path ;-)02:46
wolfspra1lyes and that is probably why I stay with 602:46
wolfspra1lbecause I do want to keep it strictly in a "what really works today?" level02:46
wolfspra1la chip I can get easily for 7 usd is attractive...02:47
wolfspra1lbetter than the latest and greatest thing that is somewhere on digikey in sample quantity for 140 USD...02:47
wpwrakyeah, 7 seems to have that elite barrier, too02:47
wolfspra1lwhich will come down next year02:47
kristianpaulnot couting DIY !02:47
wolfspra1lbut one by one02:48
wolfspra1lI think xilinx has decided to not compete economically with the market niche of the smaller xc6 devices02:48
wolfspra1l(I mean with the 7 series)02:48
wpwrakyou'd be at the level of researchers happily announcing some breakthrough that should be useful to the general public in virtually no time. of course, ten years later, none of that has seen the light of day yet ...02:49
wolfspra1lthat means the price of the smallest xc7 will only go down slowly as forced by competition at that level (i.e. only by altera)02:49
wolfspra1land which in turn means especially the smaller xc6 devices will have a very long lifetime, that is my guess02:50
wolfspra1lwhereas the typical slx75 and bigger customer will quickly switch to xc702:50
wpwrakmaybe they also have a long debugging / yield improvement phase and don't actually want a lot of customers at the moment02:51
wolfspra1lI think industry-wide, 28nm is supply constrained right now :-)02:51
wolfspra1lall the way to Apple etc.02:51
wolfspra1land I read somewhere that Apple is trying to bully some customers out of tsmc's latest-gen processes with huge orders & investments etc :-)02:52
wpwraktime for samsung to start winning some of those lawsuits :)02:52
wolfspra1lso tsmc will build some fabs/lines/whatever just for apple02:52
wolfspra1lbut xilinx is one of tsmc's true lead customers on 28nm. anyway, all moving I think, from reading the news02:53
wolfspra1lI'm just looking at the result, and that is that the slx9 is available with no fuss for 7 USD now02:54
wolfspra1lit came down from 9 USD to 7 USD in the last 4 months alone02:54
wpwraklooks like an excellent choice for getting started with such things02:54
wolfspra1lyes agreed02:55
wolfspra1lthat's also a nice and advanced 45nm process (samsung I think)02:55
wpwraknot bad. 9 USD would still be okay for that kind of task. makes a whole PCBA (with simple things only) maybe USD 20, retail perhaps USD 50. something you could make and sell as an fpgatools reference platform.02:55
rohwpwrak: i wonder how much samsung earns per sold iphone03:40
rohsimply from providing the soc and memory etc03:41
wolfspra1land displays03:58
rohthat too? hihi03:58
wolfspra1lsoc profits must be less now after apples daring multi-billion usd ic investments in recent years03:58
wolfspra1lmemory they start investing in too, and displays as well03:58
wolfspra1lgood to have 120 billion USD in cash flying around :-)03:59
wolfspra1land naturally they don't like to feed their own competitor...03:59
lekernelazonenberg: what software did you use to make those chip floorplans?10:28
lekernelwolfspra1l: have you destroyed fpga's with broken bitstream already?10:33
lekernelsorry, missed the answer in the backlog :)10:34
wpwraklekernel: he said that he hasn't yet. he left the destructive work to xiangfu, but using direct thermal execution instead of sneaky software11:28
wolfspra1las far as I'm concerned, there is no such thing as a broken bitstream :-)12:06
wolfspra1lmaybe some bitstreams and make parts of the chip unconfigurable, yeah :-)12:07
wolfspra1lcan make12:07
wpwraka bitstream that incorporates certain killer features ....12:29
GitHub46[dmp] fallen pushed 1 new commit to master: http://git.io/Z5fyFA12:32
GitHub46dmp/master 64bf35c Yann Sionneau: First release of dmp tool12:32
GitHub68[dmp] fallen pushed 1 new commit to master: http://git.io/y_r-GQ12:57
GitHub68dmp/master 11957b6 Yann Sionneau: Add informations about how to use dmp in README.md12:57
lekernelazonenberg: tried running linux on your mips softcore yet?13:42
azonenberglekernel: no MMU17:03
azonenbergso not an option17:03
azonenbergit runs code compiled with GCC though17:03
lekernelwell i'd guess there's nommu linux for mips, no?17:07
azonenbergno idea, i havent looked17:07
azonenbergThe main thing is that it isnt on my roadmap and i haven't had the time17:07
azonenbergi'm in the middle of trying to figure out how to add all the peripherals i need for my prototype in the XC6SLX25 so i can give a demo in a month or so17:08
azonenbergwithout running out of space17:08
azonenbergBecause there is no way my artix7 board will be ready before the Jan-Feb time frame17:08
lekernelwhat do you want to demo?17:10
azonenbergHopefully? A demonstration of how the isolation capabilities of my proposed architecture will prevent compromise of the kernel or other apps if one app gets pwned17:10
azonenbergNot sure if i can pull that off in a month though17:10
lekernelah yes, that thing17:11
lekernelbtw have you heard of http://genode.org/ ?17:11
azonenbergnot yet, let's see17:12
azonenbergYeah, they're trying to solve the same problem a different way17:13
larscI don't think there is nommu linux for mips17:54
azonenbergAlso if i implement a MMU it will likely be one designed for my platform rather than stock17:57
azonenbergI'm not trying to maintain compatibility with "normal" MIPS platforms at any level other than the binary ISA17:58
azonenbergbecause that saves me the trouble of porting gcc to a new ISA17:58
Fallenousounds like a very interesting project18:37
Fallenouhave you published any paper yet on your architecture ?18:37
azonenbergFallenou: not yet18:37
azonenbergi have an unpublished draft i've bounced off a couple of people but i dont want to share it too widely until i have a demo-able prototype18:37
Fallenoui'm looking forward to reading about it when it's out there :)18:37
Fallenouhi Alarm !18:38
Fallenoulekernel: what was the purpose of "plasma" in the democomp software?19:57
lekernelhuh that's old20:13
lekernelsomething a bit like that: https://www.google.com/search?q=plasma+effect20:14
Fallenouoh ok20:18
Fallenouif I find a cable VGA male <-> DVI male I should be able to connect the M1 VGA output to my monitor's DVI input, right ?20:19
Fallenoucause DVI still has analog pins20:19
Fallenouso in theory, this http://www.amazon.fr/Adaptateur-VGA-Femelle-Male-12-03-3105/dp/B000A0C1ZW/ref=acc_glance_computers_ai_ps_t_4 and a normal VGA cable20:23
larscif your monitor supports it20:30
larscbut it should I guess20:30
Fallenouok, if the adaptor does not work, I can still use the VGA cable plugged on my TV which has native VGA input support :)20:40
wpwrakthere's also DVI-D, which doesn't use the analog pins. it appears occasionally on the host side, but i'm not sure if it's common on the monitor side.21:12
Fallenouok let's hope my monitor likes analog stuff :)21:34
Fallenougn8 here !21:34
AlarmI compile with make-C Flickernoise compile-Flickernoise flickernoise.fbi. I get an error with `rtems_shell_init_env '. See http://pastebin.com/veRjG7cg21:56
johndmcmasterlekernel: hey22:07
lekernelhi johndmcmaster22:18
johndmcmasterlekernel: I just wanted to touch base from replying to your e-mail to know if you needed any more info or such from me22:19
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