#milkymist IRC log for Saturday, 2012-10-27

wpwraklekernel: at 35 kV, the stuff may just disdainfully arc over your puny little resistors :)04:38
lekernelwpwrak: sure... so put a lot of them07:23
lekernelmwalle: yes, or you can try the xilinx forums too07:24
azonenbergI think xilinx may have a winner with the 7 series if they can get yields up07:30
azonenberghttp://i.imgur.com/Pu4no.png07:30
azonenbergFloorplan of the XC6SLX25, what's the first thing that strikes you?07:31
azonenbergThe GTP qaud is eating a huge hole in the upper left of the array07:34
azonenbergAnd there are just a few lonely CLBs stuck in the upper left07:34
azonenbergI've seen that the xilinx P&R toolchain has a very annoying habit of putting timing-critical logic up in that corner07:35
azonenbergWhere it cannot really route to... anything... efficiently07:35
azonenbergi hate floorplanning designs manually but i've had to do it several times to force it to not split things from that corner out to other spots07:36
azonenbergBy comparison the XC7A100T http://i.imgur.com/cvvZT.png07:36
azonenbergnice rectangular cutous, one in the top and one in the bottom, for the GTPs07:36
azonenbergthen a smaller cutout behind the top one for the PCIe endpoint block07:37
azonenbergno small fingers of CLBs with difficulty routing to other stuff07:37
azonenbergthough i am worried that the block on the center left side by the IOBs behind the XADC etc could become a similar chokepoint07:38
azonenbergon a larger scale07:38
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