| wpwrak | lekernel: at 35 kV, the stuff may just disdainfully arc over your puny little resistors :) | 04:38 |
|---|---|---|
| lekernel | wpwrak: sure... so put a lot of them | 07:23 |
| lekernel | mwalle: yes, or you can try the xilinx forums too | 07:24 |
| azonenberg | I think xilinx may have a winner with the 7 series if they can get yields up | 07:30 |
| azonenberg | http://i.imgur.com/Pu4no.png | 07:30 |
| azonenberg | Floorplan of the XC6SLX25, what's the first thing that strikes you? | 07:31 |
| azonenberg | The GTP qaud is eating a huge hole in the upper left of the array | 07:34 |
| azonenberg | And there are just a few lonely CLBs stuck in the upper left | 07:34 |
| azonenberg | I've seen that the xilinx P&R toolchain has a very annoying habit of putting timing-critical logic up in that corner | 07:35 |
| azonenberg | Where it cannot really route to... anything... efficiently | 07:35 |
| azonenberg | i hate floorplanning designs manually but i've had to do it several times to force it to not split things from that corner out to other spots | 07:36 |
| azonenberg | By comparison the XC7A100T http://i.imgur.com/cvvZT.png | 07:36 |
| azonenberg | nice rectangular cutous, one in the top and one in the bottom, for the GTPs | 07:36 |
| azonenberg | then a smaller cutout behind the top one for the PCIe endpoint block | 07:37 |
| azonenberg | no small fingers of CLBs with difficulty routing to other stuff | 07:37 |
| azonenberg | though i am worried that the block on the center left side by the IOBs behind the XADC etc could become a similar chokepoint | 07:38 |
| azonenberg | on a larger scale | 07:38 |
| --- Sun Oct 28 2012 | 00:00 | |
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