Fallenou | ISim> restart | 07:48 |
---|---|---|
Fallenou | ISim> init | 07:48 |
Fallenou | Simulator is doing circuit initialization process. | 07:48 |
Fallenou | XXXX 2 3 | 07:48 |
Fallenou | Finished circuit initialization process. | 07:48 |
Fallenou | that's what I get mwalle larsc | 07:48 |
larsc | funny | 07:56 |
larsc | so lm32 clog2 is catucall clog2 + 1? | 07:56 |
larsc | actually | 07:56 |
Fallenou | you need to do "-1" | 07:56 |
Fallenou | ah yes so if now your clog2 is correct, I guess you have an extra "-1" | 07:57 |
Fallenou | the line is clog2(bytes_per_line)-1-2 | 07:58 |
Fallenou | -2 because you do 4 bytes accesses with WB | 07:59 |
Fallenou | and -1 because clog2 is wrong | 07:59 |
larsc | that would explain it | 08:01 |
Fallenou | totally | 08:01 |
Fallenou | that explains mwalle sees only 2 wishbone accesses instead of 4 | 08:01 |
larsc | I wonder why the -1 is not done inside the function | 08:04 |
larsc | there is a clogb2_v1 which does it as far as i can see | 08:04 |
Fallenou | I think I never got it to work | 08:05 |
larsc | clogb2_v1? | 08:07 |
Fallenou | yes, I might have tried it, but since I am still using clog2 I guess it was not working | 08:08 |
Fallenou | not sure though | 08:08 |
larsc | another option would be to replace the value > 0 with value > 1 in clog2, wouldn't it? | 08:12 |
Fallenou | brb coffee | 08:16 |
mwalle | ah funny | 08:48 |
mwalle | good that i asked :) | 08:48 |
mwalle | the real fix is to replace that function by a builtin one, see https://github.com/mwalle/milkymist/commit/a083cfea0c1f9690bbf97f069f6b56389a482151 | 08:49 |
Fallenou | you are using iverilog, right ? | 08:52 |
mwalle | yeah, but ise should support that too | 08:53 |
Fallenou | wow they waited for 14.1 to fix such a thing ... | 08:53 |
Fallenou | amazing | 08:53 |
mwalle | but that still doesnt fix my problem ;) | 08:54 |
mwalle | i already removed the the -1 from all clog2 calls | 08:54 |
Fallenou | ah ok I was not understanding why you still have the "-1" in your commit | 08:55 |
Fallenou | so now you got rid of it | 08:55 |
Fallenou | so now you should have addr_offset_width == 2 , right ? | 08:55 |
mwalle | probably, tried it yesterday, cant remember ;) | 08:57 |
mwalle | Fallenou: could you send me a vcd (isim parameter -vcdfile out.vcd) from the first few cycles, where the icache is filling and some later instructions loads hit the cache? | 08:58 |
mwalle | Quartus II 9.1 supports the built-in $clog2 function from Verilog 2005 | 09:01 |
mwalle | so altera should be fine too | 09:01 |
mwalle | and nobody uses lattice *fg* | 09:01 |
mwalle | mh does lattice even have an own synthesizer? | 09:04 |
mwalle | or do they always use synplify? | 09:04 |
lekernel | mwalle: don't use 'x', it only allows for minor synthesis optimizations and can easily waste your time with weird bugs and/or simulation/synthesis mismatches | 09:05 |
mwalle | lekernel: that was found in the lm32 source ;) | 09:06 |
mwalle | and i wondered what the reason could be to assign 'x' to a register when it is reset | 09:07 |
lekernel | what it means for the synthesizer is it will reset that register to the value/equation that causes the least logic to be used | 09:07 |
lekernel | since S6 flip-flops have a dedicated reset pin, I guess this disables reset completely | 09:07 |
mwalle | lekernel: and if i dont reset that at all?, eg omit the line in the reset case? | 09:07 |
lekernel | that's fine if you don't have any code that depends on the reset value (and you probably don't, since it works with 'x') | 09:08 |
Fallenou | mwalle: will try to send you the VCD this afternoon | 09:09 |
mwalle | mh so i still have no reason why lattice put that into the source code :| | 09:09 |
mwalle | s/reason/explanantion/ | 09:10 |
lekernel | maybe a coding style rule such as: "all registers should have a reset section" | 09:10 |
Fallenou | well it works for me using ISim | 09:10 |
lekernel | oh and | 09:10 |
Fallenou | ah you mean the 'x', yeah I don't know | 09:10 |
mwalle | lekernel: yeah that would also be my guess | 09:10 |
lekernel | isn't there a risk that latches be generated when LM32 is configured for asynchronous reset and that line is not present? | 09:11 |
lekernel | what would that do? http://pastebin.com/PBrYmnPe | 09:13 |
Action: lekernel almost never uses async reset | 09:14 | |
lekernel | hmm, no, I guess that works. so it's probably just coding style. | 09:16 |
mwalle | mh, sensitivity on posedge rst, is a noop, so should be the same like there is just 'posedge clk' as sensitivity list, shouldnt it? | 09:18 |
lekernel | yes | 09:19 |
mwalle | bbl | 09:19 |
Action: Fallenou just had lunch with Alarm | 12:30 | |
Fallenou | he's a teacher in a French electronic high school | 12:30 |
Fallenou | he would like to set up a workshop for his students using the M1 :) | 12:31 |
Fallenou | that's pretty cool | 12:31 |
Fallenou | he already has two complete Milkymist One box (with DMX spot, camera etc) | 12:31 |
larsc | I was first confused a bit, because I though you had a firealarm during lunch ;) | 12:35 |
Fallenou | ahah | 12:51 |
larsc | but, yea I should have noted the capital A | 12:53 |
lekernel | hey, is there anyone for whom http://ehsm.net/ doesn't work? | 13:05 |
lekernel | (the website) | 13:05 |
xian9fu | works fine here. 'exceptionally hard and soft meeting *2012 December 28-30 Berlin' | 13:19 |
Grievre | Is navre abandoned? | 13:27 |
lekernel | it serves it purpose, which is to control the M1 USB ports (and not be a friendly full avr softcore) | 13:37 |
lekernel | its purpose | 13:37 |
lekernel | it's not abandoned, if you send a patch to the list i'll review it | 13:38 |
Fallenou | the website works fine for me lekernel (ehsm) | 14:10 |
Grievre | lekernel: also the opencores svn browse goes nowhere useful. This isn't your fault/responsibility but I was wondering if the solution was well-known | 14:11 |
larsc | lekernel: A few days ago ehsm.net did not work, now it works fine though | 14:21 |
lekernel | Grievre: all milkymist source is on github, not OC | 14:21 |
Grievre | lekernel: oh, where's the navre code hiding? | 15:36 |
lekernel | https://github.com/milkymist/milkymist/tree/master/cores/softusb | 15:37 |
Grievre | oh, obviously | 15:38 |
kristianpaul | is m1 abandoned i sent a patch for expand csr 1 bit but.. :( | 15:38 |
kristianpaul | ?¿ | 15:38 |
kristianpaul | m1 soc* | 15:38 |
kristianpaul | sorry | 15:38 |
Grievre | the whole core is a single .v file o.o | 15:39 |
Grievre | I can see the advantage to that but it seems like it would make testing difficult | 15:40 |
lekernel | kristianpaul: this feature is in -ng, what are you complaining about? :) | 15:40 |
kristianpaul | is not in soc | 15:44 |
kristianpaul | and yes i complain because you dont seem care about m1 legacy soc | 15:44 |
kristianpaul | and just push push ans push about -ng but dont hear about more about | 15:45 |
kristianpaul | but is okay i just wanted to say hello ;) | 15:45 |
larsc | kristianpaul: fork it! | 16:18 |
--- Fri Oct 26 2012 | 00:00 |
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