#milkymist IRC log for Thursday, 2012-10-25

FallenouISim> restart07:48
FallenouISim> init07:48
FallenouSimulator is doing circuit initialization process.07:48
FallenouXXXX           2           307:48
FallenouFinished circuit initialization process.07:48
Fallenouthat's what I get mwalle larsc07:48
larscso lm32 clog2 is catucall clog2 + 1?07:56
Fallenouyou need to do "-1"07:56
Fallenouah yes so if now your clog2 is correct, I guess you have an extra "-1"07:57
Fallenouthe line is clog2(bytes_per_line)-1-207:58
Fallenou-2 because you do 4 bytes accesses with WB07:59
Fallenouand -1 because clog2 is wrong07:59
larscthat would explain it08:01
Fallenouthat explains mwalle sees only 2 wishbone accesses instead of 408:01
larscI wonder why the -1 is not done inside the function08:04
larscthere is a clogb2_v1 which does it as far as i can see08:04
FallenouI think I never got it to work08:05
Fallenouyes, I might have tried it, but since I am still using clog2 I guess it was not working08:08
Fallenounot sure though08:08
larscanother option would be to replace the value > 0 with value > 1 in clog2, wouldn't it?08:12
Fallenoubrb coffee08:16
mwalleah funny08:48
mwallegood that i asked :)08:48
mwallethe real fix is to replace that function by a builtin one, see https://github.com/mwalle/milkymist/commit/a083cfea0c1f9690bbf97f069f6b56389a48215108:49
Fallenouyou are using iverilog, right ?08:52
mwalleyeah, but ise should support that too08:53
Fallenouwow they waited for 14.1 to fix such a thing ...08:53
mwallebut that still doesnt fix my problem ;)08:54
mwallei already removed the the -1 from all clog2 calls08:54
Fallenouah ok I was not understanding why you still have the "-1" in your commit08:55
Fallenouso now you got rid of it08:55
Fallenouso now you should have addr_offset_width == 2 , right ?08:55
mwalleprobably, tried it yesterday, cant remember ;)08:57
mwalleFallenou: could you send me a vcd (isim parameter -vcdfile out.vcd) from the first few cycles, where the icache is filling and some later instructions loads hit the cache?08:58
mwalleQuartus II 9.1 supports the built-in $clog2 function from Verilog 200509:01
mwalleso altera should be fine too09:01
mwalleand nobody uses lattice *fg*09:01
mwallemh does lattice even have an own synthesizer?09:04
mwalleor do they always use synplify?09:04
lekernelmwalle: don't use 'x', it only allows for minor synthesis optimizations and can easily waste your time with weird bugs and/or simulation/synthesis mismatches09:05
mwallelekernel: that was found in the lm32 source ;)09:06
mwalleand i wondered what the reason could be to assign 'x' to a register when it is reset09:07
lekernelwhat it means for the synthesizer is it will reset that register to the value/equation that causes the least logic to be used09:07
lekernelsince S6 flip-flops have a dedicated reset pin, I guess this disables reset completely09:07
mwallelekernel: and if i dont reset that at all?, eg omit the line in the reset case?09:07
lekernelthat's fine if you don't have any code that depends on the reset value (and you probably don't, since it works with 'x')09:08
Fallenoumwalle: will try to send you the VCD this afternoon09:09
mwallemh so i still have no reason why lattice put that into the source code :|09:09
lekernelmaybe a coding style rule such as: "all registers should have a reset section"09:10
Fallenouwell it works for me using ISim09:10
lekerneloh and09:10
Fallenouah you mean the 'x', yeah I don't know09:10
mwallelekernel: yeah that would also be my guess09:10
lekernelisn't there a risk that latches be generated when LM32 is configured for asynchronous reset and that line is not present?09:11
lekernelwhat would that do? http://pastebin.com/PBrYmnPe09:13
Action: lekernel almost never uses async reset09:14
lekernelhmm, no, I guess that works. so it's probably just coding style.09:16
mwallemh, sensitivity on posedge rst, is a noop, so should be the same like there is just 'posedge clk' as sensitivity list, shouldnt it?09:18
Action: Fallenou just had lunch with Alarm12:30
Fallenouhe's a teacher in a French electronic high school12:30
Fallenouhe would like to set up a workshop for his students using the M1 :)12:31
Fallenouthat's pretty cool12:31
Fallenouhe already has two complete Milkymist One box (with DMX spot, camera etc)12:31
larscI was first confused a bit, because I though you had a firealarm during lunch ;)12:35
larscbut, yea I should have noted the capital A12:53
lekernelhey, is there anyone for whom http://ehsm.net/ doesn't work?13:05
lekernel(the website)13:05
xian9fuworks fine here. 'exceptionally hard and soft meeting *2012 December 28-30 Berlin'13:19
GrievreIs navre abandoned?13:27
lekernelit serves it purpose, which is to control the M1 USB ports (and not be a friendly full avr softcore)13:37
lekernelits purpose13:37
lekernelit's not abandoned, if you send a patch to the list i'll review it13:38
Fallenouthe website works fine for me lekernel (ehsm)14:10
Grievrelekernel: also the opencores svn browse goes nowhere useful. This isn't your fault/responsibility but I was wondering if the solution was well-known14:11
larsclekernel: A few days ago ehsm.net did not work, now it works fine though14:21
lekernelGrievre: all milkymist source is on github, not OC14:21
Grievrelekernel: oh, where's the navre code hiding?15:36
Grievreoh, obviously15:38
kristianpaulis m1 abandoned i sent a patch for expand csr 1 bit but.. :(15:38
kristianpaulm1 soc*15:38
Grievrethe whole core is a single .v file o.o15:39
GrievreI can see the advantage to that but it seems like it would make testing difficult15:40
lekernelkristianpaul: this feature is in -ng, what are you complaining about? :)15:40
kristianpaulis not in soc15:44
kristianpauland yes i complain because you dont seem care about m1 legacy soc15:44
kristianpauland just push push ans push about -ng but dont hear about more about15:45
kristianpaulbut is okay i just wanted to say hello ;)15:45
larsckristianpaul: fork it!16:18
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