#milkymist IRC log for Wednesday, 2012-10-24

mwallewpwrak: well actually its more accurate ;)06:43
mwallewpwrak: but yes, there is still many things (including some legend)06:45
mwallebut feedback is welcome, eg what does confuse you? just that its different form the lattice one?06:46
wpwrakmost of all, what the signals mean/do. also, most of them are inputs without corresponding outputs.06:49
mwallewpwrak: btw do you actually sleep? :)07:04
mwalleas i said, thats the dataflow, the controls are still missing, as is the bypass network, i guess they deserve an own sheet07:06
azonenbergmwalle: lol if lm32's forwarding is as complex as the MIPS-based softcore i'm working with for my thesis it needs a page at least07:10
wpwrak(sleep) yeah, i saw that you wrote some 3 minutes before my reply. i had just gotten up :)07:10
mwalleazonenberg: imho there should be one sheet, which gives a rough overview, whats happening07:13
azonenbergActually, now that i look at things, my forwarding isn't as bad as i remember07:13
azonenberg116 lines including the BSD license header and comments and whitespace07:13
azonenbergthe actual logic doesn't even start until line 86, the rest is signal declarations and header comments07:14
azonenbergfits in one screen07:14
wpwrakall of the form a1=(a&b&c&d&e)||(f&g&h&i)... ? :)07:15
azonenberglol no :P07:15
azonenbergthat's the public version of the codebase which is a few months out of date, i'm now developing on a private branch and will merge back when i publish my thesis07:16
azonenbergdont want to give away all of my secrets before the paper is ready :P07:16
azonenbergbut that file i dont think has changed much, if at all, since07:17
wpwrakthe code is too readable. someone could figure out what it does :)07:17
azonenbergThe CPU is nothing particularly new07:17
azonenbergi just couldnt find any open-source MIPS-1 implementations that were well documented so i had to make one07:18
azonenbergbut all of the NoC stuff etc is where my real research is at07:18
azonenbergThe CPU was a half-semester project just to kick things off07:18
wpwrak"couldn't find any decent batteries. so i built me a fusion generator."07:18
azonenbergLol hey, it gets the job done07:18
azonenbergit runs at 80 MHz in spartan6 without me even attempting to tune for performance, 5-stage pipeline, runs code compiled by unmodified mipsel-elf gcc, and is BSD licensed07:19
azonenbergno MMU but it will be getting one shortly07:20
wpwrakneat :)07:20
azonenbergThe fun part obviously is here http://code.google.com/p/utica-softcore/source/browse/trunk/hdl/achd-soc/UticaCPUExecuteStage.v07:20
azonenbergThe only file in the project more than 1k lines07:20
azonenbergi tried to keep it nice and modular07:20
azonenbergbut yeah, all of the fun work lately has been NoC and CPU-NoC integration07:22
wpwrakis "utica" an acronym or do you like tunesia ?07:31
mwalleazonenberg: the bypassing/forwarding in lm32 is rather simple07:35
azonenbergwpwrak: it's actually named after a nearby city07:36
azonenbergas are all of the simple 8/16 bit cores i made to learn verilog07:37
FallenouHi !07:37
lekernelhi wolfspraul & all07:59
mwallehttp://walle.cc/lm32-pipe.pdf updated17:13
mwallewpwrak: still only data flow ;)17:22
Fallenouhi mwalle I received your email, as soon as I have a few minutes I will do it :)17:29
Fallenoudo you doubt the simulation will ever run if I disable icache?17:29
Fallenouif the simulation runs well, what do you want me to look at?17:30
mwallepc_* :)17:34
Fallenouok ! =)17:40
mwalleesp. related to the clock, eg if there is a stall somewhere17:41
mwalleah and i_cyc_o17:42
Fallenoumwalle: looks nice ! much more precise than the previous one18:32
Action: Fallenou disabled icache and mmu and tries to run simulation18:33
Fallenouit's been a while since I last tried to run it without mmu :) so I have a few compilation errors =)18:33
Action: Fallenou adds more ifdef18:33
Fallenouok it runs!18:34
Fallenoucode runs, uart works and it prints stuff =)18:35
Fallenouso, looking at wires right now18:35
Fallenoumwalle : http://img15.hostingpics.net/pics/358365lm32screenshot.png18:49
Fallenouhere you go18:49
Fallenoutell me if you miss some piece of informatio,n18:49
Fallenoudon't pay attention to wishbone latencies, they are random18:50
Fallenouso it's normal if some wishbone transactions are faster than others18:50
wpwrakmwalle: looking better by the minute :)18:56
larscnot bad19:03
mwalleFallenou: have a look why stall_x is asserted please19:04
mwalleFallenou: btw is there an vcd export? (maybe of a given range)19:04
mwalleerr, stall_m19:06
mwalleahh lol19:07
mwalleFallenou: nevermind :) i found the signal, i was looking for19:07
Fallenougreat !19:07
mwalleCFG_SIZE_OVER_SPEED << what might this be19:08
mwalle"over speed", aha ;)19:08
Fallenouit's not defined19:09
mwalleyeah of course its not, the code is cluttered with such things19:10
Fallenouhard to read, a lot of "generate" and "ifdef"19:11
mwallebbl, supper19:12
Fallenougood apetite !19:12
mwallebut you get used to it ;)19:12
Fallenouunfortunately there is no VCD export button in the GUI19:13
Fallenoubut I think you can generate a VCD using the ISim shell prompt19:13
FallenouI've never done it though19:13
GitHub194[milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Zry4Vw19:23
GitHub194[milkymist-mmu-simulation/master] Fix compilation with MMU disabled - Yann Sionneau19:23
GitHub32[milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Kt6yxQ19:36
GitHub32[milkymist-mmu-simulation/master] Fix typo - Yann Sionneau19:36
GitHub72[milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Lhn4mQ19:56
GitHub72[milkymist-mmu-simulation/master] Make simulation silent when verbose mode is not activated - Yann Sionneau19:56
GitHub104[milkymist-mmu-simulation] fallen pushed 2 new commits to master: http://git.io/XXMIwg20:09
GitHub104[milkymist-mmu-simulation/master] Removes a few display forgotten in previous commit - Yann Sionneau20:09
GitHub104[milkymist-mmu-simulation/master] Add support for "Draw Me a Pipeline" tool in CPU simulation - Yann Sionneau20:09
mwalleah cool, at least without i cache enabled, the simulation seems to work with iverilog21:29
Fallenouoh :)21:29
Fallenouvery nice !21:29
mwalleFallenou: do you remember if you added some initializations in the icache/instruction unit?21:30
mwalle375     if (rst_i == `TRUE)21:31
mwalle376     begin21:31
mwalle377         state <= `LM32_IC_STATE_FLUSH_INIT;21:31
mwalle378         flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};21:31
mwalle379         refill_address <= {`LM32_PC_WIDTH{1'bx}};21:31
mwalle380         restart_request <= `FALSE;21:31
mwalle381     end21:31
mwallerefill_address is strange, i saw you changed that to 1'b021:32
mwallelekernel: does this even make sense?21:32
mwalleto say set this value to dont care on reset? :)21:32
Fallenouto me it is a bug, at least for simulation21:35
Fallenouin FPGA it's not a problem I guess21:35
Fallenoucause x must mean 0 or 121:35
Fallenoubut in simulation it's a problem to have a "x" value, it will make all logical operation fail :/21:35
mwalleyeah but why do i reset a register to 'dont care'?21:36
larscmwalle: it's not dont care, it's unkown21:36
Fallenouwell IMO you should not21:36
larscfor case 'x' is don't care, for assignments it is unkown21:36
mwallelarsc: sure? read it as, i dont care for this bit, let the synthesizer figure out the best value for it?21:37
Action: Fallenou would say like larsc but not sure21:37
mwalleanyways, if its unknown or don't care, why should i use that in a reset?21:38
larscit makes sense for simulation21:38
Fallenoularsc: well it makes sens but it also makes everything fail21:39
larscFallenou: could be a bug somewhere ;)21:39
Fallenoubecause AFAIK 0 and x == x instead of 021:39
Fallenouand 1 or x == x21:39
larscFallenou: yes, x will propagate21:40
larscthat's the point of it21:40
mwallemhh.. but 1 or 'unknown' is 121:40
Fallenouso if the cache contains 'x' you're basically screwed, it will propagate almost everywhere21:40
larscI think the intend is that the value should not be used before it has been properly initialized21:41
Fallenouso we should add a few tests for x values in a few places21:41
Fallenouthere is basically no test for x value in lm32 code afaik21:41
larscyou should not have to test for x21:42
mwalle1 || x == 121:43
mwalle0 && x == 021:43
FallenouOK I smoked something bad then21:44
Fallenousorry for the misinformation :)21:44
larsc0 | x = x and 1 & x = x21:44
mwalleyeah, because then x matters :)21:44
mwallei can only imagine that the refill_address is initialized just for completness21:46
Fallenouoh yes sure, I wasn't paying attention to operand order21:46
mwalleif you omit this line, the simulation is still uses 'unknown' (yeah in this sentence dont care makes no sense ;) and the hardware has either 0 or 121:47
larscFallenou: which memory gets initialized to all x? way_0_tag_ram?21:47
FallenouI don't remember what was wrong I fixed it when I started the project with simulations21:50
mwallemh my icache toggles between CHECK and REFILL21:53
Fallenoucheck register file values, if they are not xxx21:53
Fallenoucheck r0 value, do you put 0 in it ?21:53
Fallenouthis kind of commit as well : https://github.com/fallen/milkymist-mmu/commit/059f0bd849db41963b11a668ea454f351be3a9a521:56
mwalleFallenou: yeah r0 is zero21:57
Fallenougoing to sleep, I hope tomorrow or the day after I will be able to push "draw me a pipeline" ;)22:00
mwalleFallenou: could you do me one quick favor? :)22:00
Fallenouit depends, ask !22:01
mwalleinitial $display("XXX %d %d", addr_offset_width, addr_offset_msb) << put this in lm32_icache.v and check the output22:01
Fallenousorry i really gotta go !22:08
Fallenouwill do it tomorrow :x22:08
mwalleok, np, gn822:09
larscshouldn't those be const?22:11
mwallelarsc: yeah, but i changed the clogb2 to the builtin $clog222:15
mwallebut i'm already on another track to follow22:15
larscwhat do you get, 'XXX 1 2'?22:16
mwalleseem right i know ;)22:20
mwallegoing to bed, too22:30
mwallelarsc: (clog2) i see only two wb accesses, that would be 8 bytes, but bytes_per_line is 1622:44
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