| mwalle | wpwrak: well actually its more accurate ;) | 06:43 |
|---|---|---|
| mwalle | wpwrak: but yes, there is still many things (including some legend) | 06:45 |
| mwalle | but feedback is welcome, eg what does confuse you? just that its different form the lattice one? | 06:46 |
| wpwrak | most of all, what the signals mean/do. also, most of them are inputs without corresponding outputs. | 06:49 |
| mwalle | wpwrak: btw do you actually sleep? :) | 07:04 |
| mwalle | as i said, thats the dataflow, the controls are still missing, as is the bypass network, i guess they deserve an own sheet | 07:06 |
| azonenberg | mwalle: lol if lm32's forwarding is as complex as the MIPS-based softcore i'm working with for my thesis it needs a page at least | 07:10 |
| wpwrak | (sleep) yeah, i saw that you wrote some 3 minutes before my reply. i had just gotten up :) | 07:10 |
| mwalle | azonenberg: imho there should be one sheet, which gives a rough overview, whats happening | 07:13 |
| azonenberg | Actually, now that i look at things, my forwarding isn't as bad as i remember | 07:13 |
| azonenberg | 116 lines including the BSD license header and comments and whitespace | 07:13 |
| azonenberg | the actual logic doesn't even start until line 86, the rest is signal declarations and header comments | 07:14 |
| azonenberg | fits in one screen | 07:14 |
| wpwrak | all of the form a1=(a&b&c&d&e)||(f&g&h&i)... ? :) | 07:15 |
| azonenberg | lol no :P | 07:15 |
| azonenberg | http://code.google.com/p/utica-softcore/source/browse/trunk/hdl/achd-soc/UticaCPUPipelineForwarding.v#77 | 07:15 |
| azonenberg | that's the public version of the codebase which is a few months out of date, i'm now developing on a private branch and will merge back when i publish my thesis | 07:16 |
| azonenberg | dont want to give away all of my secrets before the paper is ready :P | 07:16 |
| azonenberg | but that file i dont think has changed much, if at all, since | 07:17 |
| wpwrak | the code is too readable. someone could figure out what it does :) | 07:17 |
| azonenberg | Lol | 07:17 |
| azonenberg | The CPU is nothing particularly new | 07:17 |
| azonenberg | i just couldnt find any open-source MIPS-1 implementations that were well documented so i had to make one | 07:18 |
| wpwrak | ;-) | 07:18 |
| azonenberg | but all of the NoC stuff etc is where my real research is at | 07:18 |
| azonenberg | The CPU was a half-semester project just to kick things off | 07:18 |
| wpwrak | "couldn't find any decent batteries. so i built me a fusion generator." | 07:18 |
| azonenberg | Lol hey, it gets the job done | 07:18 |
| azonenberg | it runs at 80 MHz in spartan6 without me even attempting to tune for performance, 5-stage pipeline, runs code compiled by unmodified mipsel-elf gcc, and is BSD licensed | 07:19 |
| azonenberg | no MMU but it will be getting one shortly | 07:20 |
| wpwrak | neat :) | 07:20 |
| azonenberg | The fun part obviously is here http://code.google.com/p/utica-softcore/source/browse/trunk/hdl/achd-soc/UticaCPUExecuteStage.v | 07:20 |
| azonenberg | The only file in the project more than 1k lines | 07:20 |
| azonenberg | i tried to keep it nice and modular | 07:20 |
| azonenberg | but yeah, all of the fun work lately has been NoC and CPU-NoC integration | 07:22 |
| wpwrak | is "utica" an acronym or do you like tunesia ? | 07:31 |
| mwalle | azonenberg: the bypassing/forwarding in lm32 is rather simple | 07:35 |
| azonenberg | wpwrak: it's actually named after a nearby city | 07:36 |
| azonenberg | as are all of the simple 8/16 bit cores i made to learn verilog | 07:37 |
| Fallenou | Hi ! | 07:37 |
| lekernel | hi wolfspraul & all | 07:59 |
| Fallenou | morning | 08:06 |
| mwalle | http://walle.cc/lm32-pipe.pdf updated | 17:13 |
| mwalle | wpwrak: still only data flow ;) | 17:22 |
| Fallenou | hi mwalle I received your email, as soon as I have a few minutes I will do it :) | 17:29 |
| Fallenou | do you doubt the simulation will ever run if I disable icache? | 17:29 |
| Fallenou | if the simulation runs well, what do you want me to look at? | 17:30 |
| mwalle | pc_* :) | 17:34 |
| Fallenou | ok ! =) | 17:40 |
| mwalle | esp. related to the clock, eg if there is a stall somewhere | 17:41 |
| mwalle | ah and i_cyc_o | 17:42 |
| Fallenou | mwalle: looks nice ! much more precise than the previous one | 18:32 |
| Action: Fallenou disabled icache and mmu and tries to run simulation | 18:33 | |
| Fallenou | it's been a while since I last tried to run it without mmu :) so I have a few compilation errors =) | 18:33 |
| Action: Fallenou adds more ifdef | 18:33 | |
| Fallenou | ok it runs! | 18:34 |
| Fallenou | code runs, uart works and it prints stuff =) | 18:35 |
| Fallenou | so, looking at wires right now | 18:35 |
| Fallenou | mwalle : http://img15.hostingpics.net/pics/358365lm32screenshot.png | 18:49 |
| Fallenou | here you go | 18:49 |
| Fallenou | tell me if you miss some piece of informatio,n | 18:49 |
| Fallenou | don't pay attention to wishbone latencies, they are random | 18:50 |
| Fallenou | so it's normal if some wishbone transactions are faster than others | 18:50 |
| wpwrak | mwalle: looking better by the minute :) | 18:56 |
| larsc | not bad | 19:03 |
| mwalle | Fallenou: have a look why stall_x is asserted please | 19:04 |
| Fallenou | ok | 19:04 |
| mwalle | Fallenou: btw is there an vcd export? (maybe of a given range) | 19:04 |
| mwalle | err, stall_m | 19:06 |
| mwalle | ahh lol | 19:07 |
| mwalle | Fallenou: nevermind :) i found the signal, i was looking for | 19:07 |
| Fallenou | great ! | 19:07 |
| mwalle | CFG_SIZE_OVER_SPEED << what might this be | 19:08 |
| mwalle | "over speed", aha ;) | 19:08 |
| Fallenou | ahah | 19:09 |
| Fallenou | it's not defined | 19:09 |
| mwalle | yeah of course its not, the code is cluttered with such things | 19:10 |
| Fallenou | hard to read, a lot of "generate" and "ifdef" | 19:11 |
| mwalle | bbl, supper | 19:12 |
| Fallenou | good apetite ! | 19:12 |
| mwalle | but you get used to it ;) | 19:12 |
| mwalle | thanks | 19:12 |
| Fallenou | unfortunately there is no VCD export button in the GUI | 19:13 |
| Fallenou | but I think you can generate a VCD using the ISim shell prompt | 19:13 |
| Fallenou | I've never done it though | 19:13 |
| GitHub194 | [milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Zry4Vw | 19:23 |
| GitHub194 | [milkymist-mmu-simulation/master] Fix compilation with MMU disabled - Yann Sionneau | 19:23 |
| GitHub32 | [milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Kt6yxQ | 19:36 |
| GitHub32 | [milkymist-mmu-simulation/master] Fix typo - Yann Sionneau | 19:36 |
| GitHub72 | [milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Lhn4mQ | 19:56 |
| GitHub72 | [milkymist-mmu-simulation/master] Make simulation silent when verbose mode is not activated - Yann Sionneau | 19:56 |
| GitHub104 | [milkymist-mmu-simulation] fallen pushed 2 new commits to master: http://git.io/XXMIwg | 20:09 |
| GitHub104 | [milkymist-mmu-simulation/master] Removes a few display forgotten in previous commit - Yann Sionneau | 20:09 |
| GitHub104 | [milkymist-mmu-simulation/master] Add support for "Draw Me a Pipeline" tool in CPU simulation - Yann Sionneau | 20:09 |
| mwalle | ah cool, at least without i cache enabled, the simulation seems to work with iverilog | 21:29 |
| Fallenou | oh :) | 21:29 |
| Fallenou | very nice ! | 21:29 |
| mwalle | Fallenou: do you remember if you added some initializations in the icache/instruction unit? | 21:30 |
| mwalle | 375 if (rst_i == `TRUE) | 21:31 |
| mwalle | 376 begin | 21:31 |
| mwalle | 377 state <= `LM32_IC_STATE_FLUSH_INIT; | 21:31 |
| mwalle | 378 flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; | 21:31 |
| mwalle | 379 refill_address <= {`LM32_PC_WIDTH{1'bx}}; | 21:31 |
| mwalle | 380 restart_request <= `FALSE; | 21:31 |
| mwalle | 381 end | 21:31 |
| mwalle | refill_address is strange, i saw you changed that to 1'b0 | 21:32 |
| mwalle | lekernel: does this even make sense? | 21:32 |
| mwalle | to say set this value to dont care on reset? :) | 21:32 |
| Fallenou | to me it is a bug, at least for simulation | 21:35 |
| Fallenou | in FPGA it's not a problem I guess | 21:35 |
| Fallenou | cause x must mean 0 or 1 | 21:35 |
| Fallenou | but in simulation it's a problem to have a "x" value, it will make all logical operation fail :/ | 21:35 |
| mwalle | yeah but why do i reset a register to 'dont care'? | 21:36 |
| larsc | mwalle: it's not dont care, it's unkown | 21:36 |
| Fallenou | well IMO you should not | 21:36 |
| larsc | for case 'x' is don't care, for assignments it is unkown | 21:36 |
| mwalle | larsc: sure? read it as, i dont care for this bit, let the synthesizer figure out the best value for it? | 21:37 |
| Action: Fallenou would say like larsc but not sure | 21:37 | |
| mwalle | anyways, if its unknown or don't care, why should i use that in a reset? | 21:38 |
| larsc | it makes sense for simulation | 21:38 |
| Fallenou | http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/me5cds/me95cdr.html | 21:39 |
| Fallenou | larsc: well it makes sens but it also makes everything fail | 21:39 |
| larsc | Fallenou: could be a bug somewhere ;) | 21:39 |
| Fallenou | because AFAIK 0 and x == x instead of 0 | 21:39 |
| Fallenou | and 1 or x == x | 21:39 |
| larsc | Fallenou: yes, x will propagate | 21:40 |
| larsc | that's the point of it | 21:40 |
| mwalle | mhh.. but 1 or 'unknown' is 1 | 21:40 |
| Fallenou | so if the cache contains 'x' you're basically screwed, it will propagate almost everywhere | 21:40 |
| larsc | I think the intend is that the value should not be used before it has been properly initialized | 21:41 |
| Fallenou | so we should add a few tests for x values in a few places | 21:41 |
| Fallenou | there is basically no test for x value in lm32 code afaik | 21:41 |
| larsc | you should not have to test for x | 21:42 |
| mwalle | 1 || x == 1 | 21:43 |
| mwalle | 0 && x == 0 | 21:43 |
| Fallenou | really? | 21:43 |
| mwalle | yeah | 21:43 |
| Fallenou | OK I smoked something bad then | 21:44 |
| Fallenou | sorry for the misinformation :) | 21:44 |
| larsc | 0 | x = x and 1 & x = x | 21:44 |
| mwalle | yeah, because then x matters :) | 21:44 |
| mwalle | i can only imagine that the refill_address is initialized just for completness | 21:46 |
| Fallenou | oh yes sure, I wasn't paying attention to operand order | 21:46 |
| mwalle | if you omit this line, the simulation is still uses 'unknown' (yeah in this sentence dont care makes no sense ;) and the hardware has either 0 or 1 | 21:47 |
| larsc | Fallenou: which memory gets initialized to all x? way_0_tag_ram? | 21:47 |
| Fallenou | I don't remember what was wrong I fixed it when I started the project with simulations | 21:50 |
| mwalle | mh my icache toggles between CHECK and REFILL | 21:53 |
| Fallenou | check register file values, if they are not xxx | 21:53 |
| Fallenou | check r0 value, do you put 0 in it ? | 21:53 |
| Fallenou | this kind of commit as well : https://github.com/fallen/milkymist-mmu/commit/059f0bd849db41963b11a668ea454f351be3a9a5 | 21:56 |
| Fallenou | https://github.com/fallen/milkymist-mmu/commit/d255d7c992ecda0dcb65b85e0b2b6270ca294acf | 21:57 |
| mwalle | Fallenou: yeah r0 is zero | 21:57 |
| Fallenou | going to sleep, I hope tomorrow or the day after I will be able to push "draw me a pipeline" ;) | 22:00 |
| mwalle | Fallenou: could you do me one quick favor? :) | 22:00 |
| Fallenou | it depends, ask ! | 22:01 |
| mwalle | initial $display("XXX %d %d", addr_offset_width, addr_offset_msb) << put this in lm32_icache.v and check the output | 22:01 |
| Fallenou | sorry i really gotta go ! | 22:08 |
| Fallenou | will do it tomorrow :x | 22:08 |
| Fallenou | gn8 | 22:08 |
| mwalle | ok, np, gn8 | 22:09 |
| larsc | shouldn't those be const? | 22:11 |
| mwalle | larsc: yeah, but i changed the clogb2 to the builtin $clog2 | 22:15 |
| mwalle | but i'm already on another track to follow | 22:15 |
| larsc | what do you get, 'XXX 1 2'? | 22:16 |
| mwalle | yeah | 22:20 |
| mwalle | seem right i know ;) | 22:20 |
| mwalle | going to bed, too | 22:30 |
| mwalle | gn8 | 22:30 |
| mwalle | larsc: (clog2) i see only two wb accesses, that would be 8 bytes, but bytes_per_line is 16 | 22:44 |
| --- Thu Oct 25 2012 | 00:00 | |
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