#milkymist IRC log for Friday, 2012-10-19

Fallenoumwalle: yes !07:37
Fallenouthanks for your email07:37
Action: Fallenou ping mwalle 18:43
Action: mwalle pong Fallenou18:47
mwalleseem you have a slow connection :b18:47
mwalle4 min rtt18:47
FallenouI have 100 mbps fiber optic :(18:48
Fallenoureally damn slow!18:48
mwallein france, there is fiber to the home?18:49
Fallenouyes in big cities18:49
Fallenoua few ISP do provide FTTB or FTTH18:50
mwallemom brb18:50
Action: Fallenou is asking on kernelnewbies channel if there is a linux kernel feature requiring write-only pages to be implemented in the MMU18:51
Fallenouif not, then indeed we just implement read-only, and a "permission fault" automatically means a write fault18:52
Fallenouwhich is much easier to implement18:52
Fallenouand then we don't care to fetch the faulty instruction18:52
Fallenouand indeed I think wpwrak is right, having the virtual address of the faulty instruction does not allow us to fetch the faulty instruction ^^18:53
larscFallenou: linux has no write only19:03
larscwritable always implies readable19:04
Fallenouok thanks!19:04
Fallenouso that is sorted out :)19:05
Fallenouwe don't need write-only, and therefore we don't need to check for the instruction generating the exception19:05
Fallenoumuch simpler :)19:05
Hawk777Fallenou, x86 and amd64 can't even do write-only pages19:22
Fallenouok let say we don't want to out perform x86 for now ;)19:23
wpwrak100 mbps .. that's less than one byte per second. slow indeed. good that things are simpler now :)19:28
Fallenoumaybe I should have said 100 Mbps :p19:30
wpwrakaah ! now that's quite different. a thousand million times faster :)19:33
FallenouI think itlb miss should generate an exception the same way the "Instruction Bus error" exception is generated19:59
FallenouI should have a look on this one19:59
Fallenouto see how they deal with it (delay until X stage ?)20:00
Fallenoufor data bus exception, the exception is raised right away, no delay20:00
Fallenouhum indeed they delay the exception until X stage20:01
Fallenouthey use a register to pass the "error" information through the pipeline20:01
Fallenoudecoding stage has a "bus_error_d" wire, which is passed to bus_error_x register at next pipeline cycle20:02
Fallenouand exception is only raised when bus_error_x is TRUE20:02
Fallenou(and valid_x is true as well)20:02
FallenouMy "itlb miss" information comes earlier though, at Fetch stage, but I guess I can use the same trick to propagate the information through the pipeline20:04
FallenouI just have one more propagation cycle20:04
larscwpwrak: on my companies website all the product pages have all caps titles. We do offer 3MW ADCs ;)20:15
Hawk777You need to sell 3 MW DACs. For driving speakers :)20:17
larscit acutally was a LOW POWER 3MV ADC ;)20:19
Fallenouinteresting technology!20:21
Fallenoumwalle: talk to you later, going to sleep here, a bit tired!20:22
FallenouI updated piratepad with new informations (about delaying exception and write-only not being needed) : http://piratepad.net/RSE6AWxIIa20:22
wpwraklarsc: well, everyone if moving from analog to digital. so why not do it with power, too ? :)20:25
mwallelol wpwrak :b20:30
mwallethere might be some problems with exceptions in the m stage20:31
mwallethe manual says data bus erros are imprecise20:31
mwalledata bus errors are raised in the m stage20:31
mwalleactually its the only exception raised in the m stage20:32
mwalleso if the m stage is the reason why the exception are imprecise, we'll have a problem20:34
--- Sat Oct 20 201200:00

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