| Fallenou | mwalle: yes ! | 07:37 |
|---|---|---|
| Fallenou | thanks for your email | 07:37 |
| Action: Fallenou ping mwalle | 18:43 | |
| Action: mwalle pong Fallenou | 18:47 | |
| mwalle | seem you have a slow connection :b | 18:47 |
| mwalle | 4 min rtt | 18:47 |
| Fallenou | I have 100 mbps fiber optic :( | 18:48 |
| Fallenou | really damn slow! | 18:48 |
| mwalle | in france, there is fiber to the home? | 18:49 |
| Fallenou | yes in big cities | 18:49 |
| Fallenou | a few ISP do provide FTTB or FTTH | 18:50 |
| mwalle | mom brb | 18:50 |
| Action: Fallenou is asking on kernelnewbies channel if there is a linux kernel feature requiring write-only pages to be implemented in the MMU | 18:51 | |
| Fallenou | if not, then indeed we just implement read-only, and a "permission fault" automatically means a write fault | 18:52 |
| Fallenou | which is much easier to implement | 18:52 |
| Fallenou | and then we don't care to fetch the faulty instruction | 18:52 |
| Fallenou | and indeed I think wpwrak is right, having the virtual address of the faulty instruction does not allow us to fetch the faulty instruction ^^ | 18:53 |
| larsc | Fallenou: linux has no write only | 19:03 |
| larsc | writable always implies readable | 19:04 |
| Fallenou | ok thanks! | 19:04 |
| Fallenou | so that is sorted out :) | 19:05 |
| Fallenou | we don't need write-only, and therefore we don't need to check for the instruction generating the exception | 19:05 |
| Fallenou | much simpler :) | 19:05 |
| Hawk777 | Fallenou, x86 and amd64 can't even do write-only pages | 19:22 |
| Fallenou | ok let say we don't want to out perform x86 for now ;) | 19:23 |
| wpwrak | 100 mbps .. that's less than one byte per second. slow indeed. good that things are simpler now :) | 19:28 |
| Fallenou | :) | 19:30 |
| Fallenou | maybe I should have said 100 Mbps :p | 19:30 |
| wpwrak | aah ! now that's quite different. a thousand million times faster :) | 19:33 |
| Fallenou | I think itlb miss should generate an exception the same way the "Instruction Bus error" exception is generated | 19:59 |
| Fallenou | I should have a look on this one | 19:59 |
| Fallenou | to see how they deal with it (delay until X stage ?) | 20:00 |
| Fallenou | for data bus exception, the exception is raised right away, no delay | 20:00 |
| Fallenou | hum indeed they delay the exception until X stage | 20:01 |
| Fallenou | they use a register to pass the "error" information through the pipeline | 20:01 |
| Fallenou | decoding stage has a "bus_error_d" wire, which is passed to bus_error_x register at next pipeline cycle | 20:02 |
| Fallenou | and exception is only raised when bus_error_x is TRUE | 20:02 |
| Fallenou | (and valid_x is true as well) | 20:02 |
| Fallenou | My "itlb miss" information comes earlier though, at Fetch stage, but I guess I can use the same trick to propagate the information through the pipeline | 20:04 |
| Fallenou | I just have one more propagation cycle | 20:04 |
| larsc | wpwrak: on my companies website all the product pages have all caps titles. We do offer 3MW ADCs ;) | 20:15 |
| Fallenou | ahah | 20:17 |
| Hawk777 | You need to sell 3 MW DACs. For driving speakers :) | 20:17 |
| larsc | it acutally was a LOW POWER 3MV ADC ;) | 20:19 |
| Fallenou | interesting technology! | 20:21 |
| Fallenou | mwalle: talk to you later, going to sleep here, a bit tired! | 20:22 |
| Fallenou | I updated piratepad with new informations (about delaying exception and write-only not being needed) : http://piratepad.net/RSE6AWxIIa | 20:22 |
| Fallenou | gn8! | 20:23 |
| wpwrak | larsc: well, everyone if moving from analog to digital. so why not do it with power, too ? :) | 20:25 |
| mwalle | lol wpwrak :b | 20:30 |
| mwalle | there might be some problems with exceptions in the m stage | 20:31 |
| mwalle | the manual says data bus erros are imprecise | 20:31 |
| mwalle | data bus errors are raised in the m stage | 20:31 |
| mwalle | actually its the only exception raised in the m stage | 20:32 |
| mwalle | so if the m stage is the reason why the exception are imprecise, we'll have a problem | 20:34 |
| --- Sat Oct 20 2012 | 00:00 | |
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