| lekernel | azonenberg: SFP+ modules are also pricy | 12:35 |
|---|---|---|
| azonenberg | lekernel: yes, they are | 16:07 |
| GitHub192 | [milkymist-mmu] fallen pushed 1 new commit to mmu: http://git.io/rfToPg | 17:22 |
| GitHub192 | [milkymist-mmu/mmu] Add support for page permission bits in BIOS - Yann Sionneau | 17:22 |
| mwalle | Fallenou: i think you should delay the itlb miss until the x stage | 18:25 |
| mwalle | and stall the pipeline(?) | 18:27 |
| Fallenou | hi mwalle | 21:27 |
| Fallenou | why delaying the itlb exception ? | 21:29 |
| Fallenou | I'm not sure I can stall the pipeline and let the instruction go to X stage | 21:33 |
| Fallenou | because I think that if I stall the pipeline, nothing will move anymore | 21:35 |
| Fallenou | so the instruction causing the itlb miss will stay in fetch stage, and never go to decode and execute stage | 21:35 |
| Fallenou | it seems that lm32 stalls the pipeline only when a stage needs more than 1 clock cycle to finish its job | 21:41 |
| Fallenou | for instance a cache miss stalls the pipeline during the refill through wishbone bus | 21:41 |
| Fallenou | but I can let the pipeline continue going forward but with a "kill flag" on adress/fetch/decode stage instructions | 21:42 |
| Fallenou | it's a way of saying "ok the instruction is passing by but it should not do anything" | 21:42 |
| Fallenou | it's used for instance when branch prediction failed | 21:43 |
| Fallenou | so that the fetched instruction is not executed | 21:43 |
| mwalle | see scall | 21:44 |
| mwalle | its delayed until the x stage | 21:44 |
| mwalle | i guess all exceptions are handled in the x statge | 21:44 |
| mwalle | and if you delay it, you wont have any problems with itlb miss in x stage and dtlb miss in m (?) stage at the same time | 21:45 |
| Fallenou | exception "occure" in x stage yes, that's what they say in the datasheet | 21:45 |
| Fallenou | and that's what is saved in EA | 21:45 |
| Fallenou | I should have a look on scall indeed | 21:46 |
| wpwrak | careful with additional state that's being passed along the pipeline. the more state you have, the more interesting the bugs ... :) | 21:46 |
| mwalle | f stage is where the itlb miss exception currently occurs, right? | 21:46 |
| Fallenou | yes | 21:47 |
| Fallenou | and dtlb in m stage | 21:47 |
| mwalle | so only the a stage is stalled | 21:47 |
| Fallenou | oh yes true | 21:47 |
| Fallenou | but then there is a "bubble" in the pipeline ? | 21:48 |
| Fallenou | I wonder what happens then | 21:48 |
| mwalle | right | 21:48 |
| Fallenou | I am not sure if at the moment lm32 handles this | 21:48 |
| Fallenou | if it can happen with original lm32 design | 21:48 |
| mwalle | the current instruction moves to decode stage | 21:48 |
| mwalle | then to x stage | 21:49 |
| mwalle | the exception also moves to d then x | 21:49 |
| mwalle | and is handled | 21:49 |
| mwalle | and i guess the instruction in x is killed | 21:49 |
| mwalle | or anything before x | 21:49 |
| Fallenou | anything before x | 21:49 |
| mwalle | havent looked at the exception handling, once there is one ;) | 21:50 |
| mwalle | btw what happens atm with the instruction right before that one which causes an itlb miss= | 21:51 |
| Fallenou | it gets executed (and m/w) | 21:51 |
| mwalle | is there additional logic? | 21:52 |
| Fallenou | yes a little bit | 21:52 |
| Fallenou | I have some kind of delay in fact | 21:52 |
| mwalle | ok | 21:53 |
| Fallenou | when I raise the exception it is not taken into account right away anyway | 21:53 |
| Fallenou | so the instruction in decode reaches the X stage anyway | 21:53 |
| mwalle | if you delay the exception i guess it will be consistent with the current exception handling and you wont need that delay | 21:53 |
| Fallenou | but I need to study that a little bit more | 21:53 |
| Fallenou | I'm going to sleep, I will study a bit simulations to have consistant datas | 21:54 |
| Fallenou | I'm talking by memory here | 21:54 |
| mwalle | ok gn8 | 21:54 |
| mwalle | i'll watch some lectures ;) | 21:55 |
| Fallenou | hard to have all precise informations about pipeline states in the head :) | 21:55 |
| Fallenou | see you ! gn8! | 21:55 |
| Fallenou | thanks for your feedback! | 21:55 |
| mwalle | i think its relly good explained in the lessons ;) | 21:55 |
| Fallenou | don't hesitate to answer the email as well :p | 21:55 |
| Fallenou | *zZzZ* | 21:55 |
| mwalle | tomorrow, too tired atm ;) | 21:56 |
| --- Thu Oct 18 2012 | 00:00 | |
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