#milkymist IRC log for Wednesday, 2012-10-17

lekernelazonenberg: SFP+ modules are also pricy12:35
azonenberglekernel: yes, they are16:07
GitHub192[milkymist-mmu] fallen pushed 1 new commit to mmu: http://git.io/rfToPg17:22
GitHub192[milkymist-mmu/mmu] Add support for page permission bits in BIOS - Yann Sionneau17:22
mwalleFallenou: i think you should delay the itlb miss until the x stage18:25
mwalleand stall the pipeline(?)18:27
Fallenouhi mwalle21:27
Fallenouwhy delaying the itlb exception ?21:29
FallenouI'm not sure I can stall the pipeline and let the instruction go to X stage21:33
Fallenoubecause I think that if I stall the pipeline, nothing will move anymore21:35
Fallenouso the instruction causing the itlb miss will stay in fetch stage, and never go to decode and execute stage21:35
Fallenouit seems that lm32 stalls the pipeline only when a stage needs more than 1 clock cycle to finish its job21:41
Fallenoufor instance a cache miss stalls the pipeline during the refill through wishbone bus21:41
Fallenoubut I can let the pipeline continue going forward but with a "kill flag" on adress/fetch/decode stage instructions21:42
Fallenouit's a way of saying "ok the instruction is passing by but it should not do anything"21:42
Fallenouit's used for instance when branch prediction failed21:43
Fallenouso that the fetched instruction is not executed21:43
mwallesee scall21:44
mwalleits delayed until the x stage21:44
mwallei guess all exceptions are handled in the x statge21:44
mwalleand if you delay it, you wont have any problems with itlb miss in x stage and dtlb miss in m (?) stage at the same time21:45
Fallenouexception "occure" in x stage yes, that's what they say in the datasheet21:45
Fallenouand that's what is saved in EA21:45
FallenouI should have a look on scall indeed21:46
wpwrakcareful with additional state that's being passed along the pipeline. the more state you have, the more interesting the bugs ... :)21:46
mwallef stage is where the itlb miss exception currently occurs, right?21:46
Fallenouyes21:47
Fallenouand dtlb in m stage21:47
mwalleso only the a stage is stalled21:47
Fallenouoh yes true21:47
Fallenoubut then there is a "bubble" in the pipeline ?21:48
FallenouI wonder what happens then21:48
mwalleright21:48
FallenouI am not sure if at the moment lm32 handles this21:48
Fallenouif it can happen with original lm32 design21:48
mwallethe current instruction moves to decode stage21:48
mwallethen to x stage21:49
mwallethe exception also moves to d then x21:49
mwalleand is handled21:49
mwalleand i guess the instruction in x is killed21:49
mwalleor anything before x21:49
Fallenouanything before x21:49
mwallehavent looked at the exception handling, once there is one ;)21:50
mwallebtw what happens atm with the instruction right before that one which causes an itlb miss=21:51
Fallenouit gets executed (and m/w)21:51
mwalleis there additional logic?21:52
Fallenouyes a little bit21:52
FallenouI have some kind of delay in fact21:52
mwalleok21:53
Fallenouwhen I raise the exception it is not taken into account right away anyway21:53
Fallenouso the instruction in decode reaches the X stage anyway21:53
mwalleif you delay the exception i guess it will be consistent with the current exception handling and you wont need that delay21:53
Fallenoubut I need to study that a little bit more21:53
FallenouI'm going to sleep, I will study a bit simulations to have consistant datas21:54
FallenouI'm talking by memory here21:54
mwalleok gn821:54
mwallei'll watch some lectures ;)21:55
Fallenouhard to have all precise informations about pipeline states in the head :)21:55
Fallenousee you ! gn8!21:55
Fallenouthanks for your feedback!21:55
mwallei think its relly good explained in the lessons ;)21:55
Fallenoudon't hesitate to answer the email as well :p21:55
Fallenou*zZzZ*21:55
mwalletomorrow, too tired atm ;)21:56
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