#milkymist IRC log for Monday, 2012-10-15

--- Mon Oct 15 201200:00
GitHub136[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/fecab5518bfef72105ab4ba437f0cad51fc4e6f417:33
GitHub136[migen/master] transform/unroll_sync: support generator function - Sebastien Bourdeauducq17:33
GitHub28[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/daee4fb58c94db71885bfacbded5e4b77f8f6a9318:23
GitHub28[migen/master] transform/unroll_sync: autodetect in/out - Sebastien Bourdeauducq18:23
Fallenouwhy using only 1 exception handler for both i/d tlb misses is good ?18:38
Fallenouinstead of 1 handler for each18:39
Fallenoubecause it might not be so simple to make this change18:41
FallenouIt's quite easy to keep 2 exception vectors, each calling the same C function which would then be the "unique" tlb miss exception handler18:42
Fallenoubut having only 1 exception vector is not so easy18:42
FallenouI don't know if there is a big performance problem with keeping 2 exception vectors (the 8 instructions in crt0.S)18:43
larscwhy is it complicated to make the change?18:48
Fallenoufor now I see only one problem but I don't have easy solution to solve it18:48
Fallenouin dtlb_miss_handler I need to do a addi ea, ea, -418:49
Fallenoubefore saving the registers and calling the dtlb_miss_handler18:49
Fallenouhttps://github.com/fallen/milkymist-mmu/blob/mmu/software/bios/crt0.S#L110 see there18:50
Fallenoubut since  .save_all routine saves all the registers afterward, I won't be able to make this change (ea -= 4) after save_all is called18:51
Fallenoubecause it won't do anything18:51
Fallenouat the end of the exception_handler there is the .restore_all_and_eret routine which restores all registers (and would then overwrite my ea) and then do "eret"18:51
Fallenoueret does jump to "EA"18:51
Action: Fallenou is not sure if he is clear enough18:52
larscI understand it18:52
Fallenouor maybe I need to add detection of TLB miss source in "save_all" routine, to make it do the job on EA before saving it18:52
larscor in restore_all18:54
Fallenoujust before the eret call18:55
Fallenouwould be a better idea indeed18:55
Fallenouso my question would be, what's best : doing this hack (a check on tlb miss origin in .restore_all_and_eret)? or keeping 2 exception vectors (calling the same C function)?18:56
larschard to say18:57
FallenouI don't quite remember in the first place why we wanted to only have 1 exception (vector? or handler?) for misses (and another one for permission faults)18:57
larscme neither18:57
FallenouI guess it's good for cache18:58
larscI think mwalle was pushing for it18:58
Fallenouor maybe wpwrak or both18:58
Fallenoulet's ask them :)18:58
Action: Fallenou ping ping18:58
GitHub37[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/daee4fb58c94...31cdb02eff9b19:12
GitHub37[migen/master] actorlib/spi: typo - Sebastien Bourdeauducq19:12
GitHub37[migen/master] bank/description: regprefix - Sebastien Bourdeauducq19:12
wpwrakas far as a i remember, i didn't favour any of the two choices. if separate vectors are more convenient, then i don't see a need for trying to have just one20:09
Fallenoubut then we need to have exception vector as well for permission faults20:29
Fallenoucan ITLB issue permission fault ?20:31
Fallenoudtlb can issue permission fault for read/writes ...20:32
FallenouITLB ... I don't see what permission fault it can generate ... either the page is mapped (and then we can say it's executable) or either it is not mapped (and it's a miss)20:32
Fallenouright ?20:32
Fallenouor I am missing something ?20:32
Fallenouam I*20:32
Fallenouso can we say permission fault is just about DTLB ? (and then i's easy for this problem)20:34
wpwraki think itlb and dtlb should have the same page tables. otherwise you get a lot of duplicate work. so "not mapped" to indicate "not executable" would require that the software does the checking, increasing the execution path of the handler20:35
Fallenouoh, the same page tables ???20:35
Fallenouhum I think lekernel was thinking about the contrary20:35
Fallenouthis kind of decision is a big change in the code of the mmu20:37
Fallenouso this deserves an email to the mailing list :)20:37
Fallenouso that anyone can give his opinion20:37
Fallenouso that I don't change everything for nothing :p20:37
Fallenoufor now each TLB has it's own "blockram" page table20:37
Fallenouwhich simplifies as you said the case of itlb miss which indicated the page is not mapped and then not executable20:38
Fallenouwell no, not exactly20:39
Fallenouitlb miss just indicates it's not in the "tlb" , it could be mapped, that would need a check in linux internal structures20:39
Fallenouto check if there is a mapping20:39
wpwrakwait .. the tlb shouldn't really know about page tables. the mapping page table -> tlb is done in the handler.20:40
Fallenouyes sure20:40
FallenouI just mixed up things :)20:40
Fallenouoh ok you were talking about the page table ...20:40
Fallenouindeed the same page table20:40
Action: Fallenou must be tired ...20:41
Fallenouand in the page table you have the permission rwx, if the permission x is present and itlb misses, then we update the itlb line with the correct mapping20:41
Action: Fallenou needs to think about this a little bit more20:42
FallenouI will shoot an email soon about that :)20:42
Fallenouneed to go, thanks !20:42
wpwraknp ;)20:44
--- Tue Oct 16 201200:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!