#milkymist IRC log for Wednesday, 2012-09-26

--- Wed Sep 26 201200:00
Fallenoulekernel: DDR4 is this marketing bullshit or do we earn something by using that ?17:33
Fallenouhttp://www.engadget.com/2012/09/26/final-ddr4-specification/17:33
Fallenouin term of real bandwidth17:33
FallenouI hope they don't increase latency17:33
lekernelyeah, it should be faster17:41
lekernel3.2Gbps/pin is higher than the ~1.8 of DDR3, and with more banks and the new access scheme you should increase page hit rate and make transfers more efficient than normal bursts17:43
Fallenouok, great then !17:44
lekernelof course, FPGA I/Os are still too slow to handle that *sigh*17:44
Fallenou:/17:44
lekernelif you want very fast memory look at the GDDR17:44
Fallenoulike GDDR5 ?17:44
lekernelyeah, it's 4.5Gbps/pin17:44
Fallenouwhy don't they use "GDDR" for main memory then ? what's the drawback ?17:45
lekernelit would be *great* to throw that into the M3 instead of a mess of multiple chips of DDR317:45
lekernelbut with the shitty kintex-7 I/Os you can only go to 1.8Gbps/pin17:45
lekerneland with lots of jitter17:46
lekernelif you're using those PLLs17:46
Fallenouand withVirtex 7 ? (isn't it faster ?)17:46
lekernelseriously we're talking about 150ps of jitter here... that's 27% of your timing budget lost to that crappy PLL17:47
Fallenouwow17:47
lekernelI'm tempted by adding an external clock chip with a more reasonable (< 1ps) jitter level17:47
Fallenouto have the correct frequency directly, with no PLL/DCM17:47
lekernelproblem is, in case of fuckups, PCB respins are expensive17:47
Fallenouwhy would it be more expensive ?17:48
lekernelvirtex 7 is super expensive17:48
Fallenouclock chip is harder to solder than current osc ?17:48
lekernelwell, because you're routing a lot of high speed, length matched traces between a clock chip, 8 DDR3 chips and a FPGA17:48
lekernelif you have skew, it can be harder to correct17:49
Fallenouah yes you mean you have to modify the routing17:49
lekernelthough some clock chips have multiple outputs with configurable phase... need to look at that17:49
Fallenouheh, like a DCM/PLL but on a chip17:50
Fallenouthis clock chip would replace the current osc and only be connected to the FPGA via a GCLK io ?17:51
Fallenouno direct connection to DDR , right ?17:51
Fallenouor direct connection, but skew adjustment for nets between FPGA and DDR chip ? in order to take into account the time for the clock to go through the FPGA ?17:53
lekernelwell, you'd need multiple phase aligned clocks, one for the 1.8Gbps data transfers and the other for the system (since you can't run it at 900MHz)17:53
lekernelmaybe you can get away without a direct DDR connection, yes17:54
lekernelalso, depending on how you deal with DQS, the PLL jitter might still be acceptable17:54
lekernelanyway, I'm a lot more worried about marketing than DDR3 now17:56
Fallenouyes that's what I understood17:58
Fallenouis there something new about M3 ? marketing ideas ? technical ideas ?17:59
wpwraklekernel: if you have to add a clock chip but can do it in a way that allows you not using it (either by FOGA configuration or just not soldering it), then you'd have less design risk20:00
wpwrakalso, if you market the critter for a specific purpose (e..g, video mixing), then technical specs don't matter all that much, as long as it does the job20:01
wpwrakso DDR4 is not the enemy. 4K or DVI-du-jour may be, though.20:02
lekernelyou still need a lot of memory bandwidth ...20:14
lekernelwhich GDDR5 would better provide if the FPGA I/O and PLL weren't so lousy20:15
Fallenouwpwrak: (technical specs don't matter all that  much, as long as it does the job) well yes that's something we learned through the Milkymist experience so far :)20:17
Fallenouwe don't care we are not 1 Ghz/DDR4, but we indeed would care to have 1080p and hdmi20:18
wpwrakyeah. there are two really simple questions: "does it do what it promises to do ?" and "is what it does useful for me ?"20:20
Fallenousure20:20
Fallenouand does it do as well (or better) as what I can have elsewhere ?20:21
wpwrakof course, at some point, price enters the equation too20:21
Fallenouyes20:22
wpwrakcompetition is included in the 2nd question: if the competition already does this and does it better, then what it the M3 does isn't so useful for me20:22
wpwraks/it the/the20:22
--- Thu Sep 27 201200:00

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