#milkymist IRC log for Tuesday, 2012-09-18

--- Tue Sep 18 201200:00
xiangfuhave a question about GCLK pin. when I connect a osc to GCLK pin. the jtag because un-stable. for example on 'detect' and 'pld load ...'13:02
kristianpauls/because/become =13:15
kristianpauls/=/=13:15
kristianpaul?13:15
xiangfus/because/become13:18
xiangfusorry for typo.13:18
xiangfuwhen I disconnect the GCLK pin. I can load bistream >20 times.13:18
xiangfuwhen I connect the GCLK pin to osc. the pld load became un-stable.13:18
xiangfu~3 of 20 times can be success.13:19
xiangfukristianpaul, I have improve on my mini-jtag problem. now there must be hardware problem left.13:19
xiangfuthe GCLK I mean 'IO_L30N_GCLK0_USERCCLK_2' PIN55 of slx9 chip.13:27
Fallenouis the osc "clean" ?13:27
Fallenouis the frequency the "good one" ? (is there a precise frequency to have ?)13:28
xiangfunot clean. I manually soldering the osc to a pcb. I have to connect the  2 power wires. then connect the clk wires back to fpga chip.13:33
xiangfuthe low osc get better result.13:33
xiangfuany advice on making a stable osc ? for my mini-slx9 board13:35
xiangfuthe osc and fpga chip not on same PCB. :(13:35
xiangfuI have to connect them by using a ~5CM wire.13:35
kristianpaulwait the osc is alone?13:37
kristianpaul5cm is long13:37
xiangfuyes. it's alone.13:38
kristianpaulhmm some capacitors may be missing13:39
kristianpaulby osc you mean a xtal?13:40
xiangfuI mean 'crystal'13:43
xiangfu5CM wire is too long. maybe I try to use even low osc, like 32K.14:01
kristianpaulbut add tha caps14:01
kristianpaulin paralle to the xtal ground14:02
kristianpaulor it will not resonate well  i think14:02
xiangfukristianpaul, I added 2 0.01uF caps to the power pins of crystal14:04
xiangfukristianpaul, the board is like: http://downloads.openmobilefree.net/tmp/mini-slx9-all.jpg14:16
rohhm. maybe use a osc not an xtal... more stable with such long wires14:21
xiangfuok. I am a little confuse on osc and xtal. I know there are 4 pins and 2 pins type.14:24
xiangfu(4 pins) crystal oscillate when apply a voltage.14:25
xiangfuI am a little confuse on those two English wolds.14:26
rohyeah.. they sometimes get mixed up, but i think you got it right14:27
rohmany devices can even work with both, but sometimes need correct config fuses to be set, like on avr or similar mcu14:27
xiangfus/wolds/words14:28
rohi see 2 small ceramic caps to ground on crystal in the area of 12pf-18pf on xtals and blocking caps of 10-100nF on the vcc of oscillators14:30
rohtheses osc are basically nothing but 2 inverters with a crystal, some caps and maybe a resistor in one case14:30
rohfor usecases where one has lots of load on a clock when for example multiple devices get the same clock from one source14:31
rohbut they are more expensive than a simple xtal of course14:31
xiangfuin the top-middle pcb. there are 3 osc. each osc connect one cap. one of them connect a resistor. in that picture I am using a 20M osc.14:37
xiangfuwhat should I do to improve the osc 'stable'? 1. using short wire. 2. using a low osc(like 32K etc) right?14:37
xiangfuI really hope I can make any pcb like Werner does. :-D14:38
kristianpaul:-)14:50
kristianpaulyeah14:50
xiangfukristianpaul, ok. just switched to a short wires. it do get better.14:52
wpwrakthat was roughly what came to my mind when i saw your wire chaos ;-)14:52
wpwrakat how many MHz is the osc running ?14:52
xiangfu20M14:58
xiangfu(wire chaos ) that is my routing result without using KiCAD. :-D15:00
wpwrakhmm, with your setup, that may already be too much. it's now only that you have very long signal wires but also that your ground is probably very complicated. e.g. the clock signal needs to "travel back" on ground somehow. and there's probably no direct way. so that's one thing to check: make sure you have FPGA ground and oscillator ground connected near the clock signal.15:00
wpwrakyou really ought to make your own pcb. that monster you've created may be okay for an arduino, but an fpga is a bit more complex :)15:01
kristianpaulyou can get made the one from azonenberg , i guess is cheap street work15:02
wpwrakor use the design as a basis but simplify it first. the layout is somewhat demanding (and designed for high speeds)15:06
kristianpaulyeah15:07
kristianpaulsimplify btw, if i delete footprints kicad deltec the un connected routes15:07
kristianpaulthats a plus :)15:07
kristianpauldeltec/delete15:07
xiangfuI learned a lot by making those boards. :)15:07
kristianpaulor just simply avoid the wires as much you can15:08
xiangfu(make sure you have FPGA ground and oscillator ground connected near the clock signal.) hmm.. how do I do this in my wires project?15:08
kristianpaulnot use wires :)15:09
kristianpaulconnect all in same breakout board15:09
kristianpaulnear15:09
cdelonger wires can act as antenna, usually not good15:10
Fallenouhehe :)15:12
xiangfuwhy the bad osc make jtag load bitstream un-stable?15:24
wpwrakxiangfu: you could have a ground pin and a signal pin next to each other (on both sides). when connect them, ideally with a piece of ribbon cable (that way, you can have easily two wires next to each other)15:24
wpwrakbad osc makes everything unstable :)15:24
wpwrakand maybe it's not bad osc but bad voltage. or both. e.g., the decoupling caps for fpga power, are they on the same board as the fpga ? or are they on the other side of some wire ?15:26
xiangfuthose decoupling caps on the other side of some wire.15:27
xiangfuwpwrak, (a ground pin and a signal pin next to each other) got it.15:28
wpwrakthat makes them useless. they should be millimeters away, not 10 cm15:28
xiangfu:-)15:28
xiangfuok.15:29
wpwrakxiangfu: you may want to consider getting this book: http://www.amazon.com/Circuit-Designers-Companion-Third-Edition/dp/0080971385/ref=pd_sim_sbs_b_115:30
wpwrakxiangfu: it's not an introduction. it's rather a book that tells you what goes wrong after you've done everything the introductions tell you.15:31
xiangfuwpwrak, I have read ~1000 pages English book (1.5 book, I should finish the second one). before start those work. now another ~500 pages book.15:32
wpwraksorry ;-)15:33
xiangfuwpwrak, thanks for the link.15:33
cdexiangfu: are those books also on circuit design? would you recommend them?15:33
xiangfumore books always good. :-)15:33
wpwrakbut this is a good one. it's very hands-on. and it helps to understand some of the concepts others sometimes mention without properly explaining.15:34
xiangfuwpwrak, the English book is hard for me. :-)15:34
xiangfucde, no. not on circuit design.15:34
cdeok15:35
wpwrakfor n -> infinity, diffculty of book n goes towards zero :)15:35
xiangfucde, Digital_Design_and_Computer_Architecture15:35
xiangfuthe second one is 'Semiconductor_Manufacturing_Technology'15:35
xiangfuwpwrak, :-)15:35
xiangfuwpwrak, I will read that one. thanks15:36
xiangfuwpwrak, I am writing the code that read the Configure Register Status out by using jtag. is there more registers that I can read by using jtag?15:37
xiangfuwpwrak, (ug380.pdf  P151: Configuration Register Read Procedure (JTAG))15:38
xiangfucde, this one: http://www.amazon.com/Digital-Design-Computer-Architecture-Harris/dp/012370497915:39
xiangfuwpwrak,  expensive book, compare to others.15:40
wpwrakyeah. they seem to know its value.15:41
cdethanks very much, xiangfu15:41
wpwrak(registers) here's an example for reading BOOTSTS: http://projects.qi-hardware.com/index.php/p/wernermisc/source/tree/master/m1rc3/norruption/2/bootsts15:46
wpwraksee pages 93, 102 of ug38015:46
xiangfuwpwrak, thanks15:48
--- Wed Sep 19 201200:00

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