| kristianpaul | azonenberg: Hi | 15:20 |
|---|---|---|
| kristianpaul | azonenberg: Why you wrote your own uart core for the red tin logic analizer and no re-used one from somewhere else? | 15:21 |
| Hodapp | azonenberg hangs out here? | 15:33 |
| larsc | all the cool kids do, don't they? ;) | 15:37 |
| azonenberg | kristianpaul: i wanted something simple that had a raw interface | 16:01 |
| azonenberg | rather than forcing use of wishbone or some other bus | 16:01 |
| azonenberg | like the opencores one did | 16:01 |
| azonenberg | i had written the uart a while ago for a different project anyway | 16:01 |
| azonenberg | so just dropped it in | 16:01 |
| kristianpaul | have you tried faster speeds than the 115kpbs? | 17:30 |
| sb0 | http://milkymist.org/3/migen_fpgaworld.pdf | 21:35 |
| --- Fri Aug 31 2012 | 00:00 | |
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