#milkymist IRC log for Tuesday, 2012-08-07

lekernelhmm... how does one generate and receive 1080p60 video signals? bit clock is 1485MHz, and artix-7 serdes are only 1250MHz (altera is worse)15:40
lekernelthings like http://www.nxp.com/products/interface_and_connectivity/video_serdes/ seem pretty slow too15:40
lekernel("3 lanes at 10x serialization rate up to 1.95 Gbit/s" of course, the 1.95 Gbit/s is all three channels combined)15:41
lekernelkintex has 1600MHz serdes but they are super expensive15:42
Fallenoumaybe nobody does :) maybe they do 1080i60 or 1080p3015:44
lekernelaccording to xrandr my laptop lcd is in 1080p5015:45
larscwe use a hdmi phy which does serial->parallel15:47
lekernelthings like this? http://www.siliconimage.com/products/product.aspx?pid=6615:48
lekernelThe Sil9002 discrete HDMI® PHY transmitter PHY is designed to work exclusively with Silicon Image's transmitter IP that is integrated by MPEG system-on-a-chip (SoC) silicon manufacturers.15:48
larsclekernel: http://wiki.analog.com/resources/fpga/xilinx/kc705/adv751115:48
larscour image transmitter IP is opensource15:50
larscbut it's just a dumb framebuffer15:50
lekernelah, thanks!15:51
Fallenoularsc: you work at AD ?15:51
lekernel"The ADV7511 interface consists of a 16bit YCbCr 422" huh15:52
lekernelHDMI is RGB, no?15:52
Fallenoumaybe it gets translated into rgb15:53
lekernelanyway, interesting that only adi seems to be making fast serdes ...15:53
larscFallenou: yes15:54
lekernelyes you can switch between YCbCr and RGB (ie disable the color space transform of the adi chip)15:54
Fallenounice :)15:54
larsclekernel: hdmi is both YCbCr and RGB15:54
larscthe adv7511 supports both YCbCr and RGB in and out15:54
larscand has a CSC which allows you to convert if neccessary15:55
lekernellarsc: I'd actually love a dumb bidirectional high-speed serdes. just to solve the "slow FPGA I/O" problem.15:56
lekerneleven a 1:2 serdes would do the trick15:56
lekernel(and require fewer pcb traces)15:57
larscthe adv7511 is not so dumb, input is only the video stream, but everything of the hdmi protocol is generated on the device15:58
lekernelyes, I see that, even HDCP15:59
lekernelhttp://avnetexpress.avnet.com/store/em/EMController/Xilinx/XC7K325T-1FBG676CES9919/_/R-5002959400059/A-5002959400059/An-0?action=part&catalogId=500201&langId=-1&storeId=500201&listIndex=-1&page=1&rank=516:18
lekernel$119 ?!16:18
lekernelothers are $1k-$2k16:18
lekernelthere's another one at $13716:19
lekernelalso with CES991916:19
lekernelare those 90% dysfunctional chips? :-)16:19
larschm: "1-$1,497.000" and "6-$149.7000" somebody put the decimal point at the wrong place?16:23
lekernelall CES9919 chips are much cheaper16:25
lekernelI guess they don't work16:25
lekernelthis code isn't even listed on http://www.xilinx.com/support/documentation/7_series_errata.htm16:25
larscmaybe they just list it and hope somebody buys it by accident ;)16:29
lekernelso it seems that options are16:31
lekernel1) artix-7 and 720p or 1080p30 only16:31
lekernel2) artix-7 and fat, messy and slightly expensive chips for 1080p60 (which also remove the possibility of bidirectional hdmi ports)16:31
lekernel3) very expensive kintex-716:32
lekernelfor sampling you might be able to use two serdes and 180° clocks :) but it's kinda risky16:38
lekerneland for transmitting... maybe with some external buffering/muxing... if I want to play with 1.5GHz discrete logic on a PCB ;)16:41
Alarmgit clone git://github.com/fallen/rtems-milkymist.git is dead ?19:23
kristianpaulmigrated19:24
kristianpaulupstream19:24
Alarmupstream = ?19:34
larscmerged in the rtems project19:35
larscrtems.org19:35
Alarmok19:35
lekernelroh: does bootlab still exist?20:19
lekernelhey Lattice has 3200MHz SERDES20:49
lekernelhttp://www.latticesemi.com/documents/ds1021ea.pdf20:49
lekernelunless I read it wrong ...20:50
Fallenouhey I have an ECP3 board :)20:52
lekerneldo they still sell them for cheap?20:54
Fallenouit was $9920:54
Fallenouthe versa kit20:55
Fallenoudunno if they still sell them20:55
lekernelit's $299 now20:55
Fallenouhum yep price gone up again20:56
Fallenouwould you switch to lattice ? :)20:56
lekernelhow's the software? I tried it a few years ago and it was much worse than ISE20:56
Fallenouwell it's an ISE clone20:56
FallenouI see almost no difference except the name20:57
FallenouI had to use windows IIRC to flash the board20:57
Fallenouin a virtualbox it worked fine20:58
lekernelazonenberg: you there?20:58
azonenberglekernel: yep20:58
azonenbergThis is probably a better forum for this discussion than FB :P20:58
lekernelas far I know the S6 transceivers work indeed to 3+GHz, but only with signals that have an embedded clock20:59
azonenberganyway so have you considered using spartan6 lxt serdes?20:59
azonenbergYou're transmitting, right?20:59
lekernelserdes != transceiver20:59
azonenbergor do you need to receive too20:59
lekernelat least in xilinx terminology. now it could be that lattice calls serdes what xilinx calls transceiver20:59
azonenbergwhats the difference? I know the GTPs can do clock recovery and the s6 serdes cannot21:00
azonenbergis that it?21:00
azonenbergbut "can do" and "must do" arent the same thing21:00
lekernelyes, but can this clock recovery be disabled?21:00
lekerneland use a supplied clock instead?21:00
lekernelAFAIK in S6 the SERDES use an I/O clock generated by PLL+BUFPLL21:01
lekerneland the GTP contain their own PLL, recover clock from the incoming signal, and transfer the data to the fabric/user clock with built-in FIFOs and such21:02
azonenberghmm, interesting21:02
azonenbergso the gtp is a serdes + clock recovery + other stuff21:02
azonenbergi've never used them21:02
lekernelI think you cannot clock the GTP from anything else than its built-in PLL that locks on the incoming signal, but I might be wrong21:03
azonenbergi looked briefly at IOSERDES21:03
lekerneland yes, the GTPs are big and complex beasts21:04
azonenbergBut again, refresh my memory21:05
azonenbergwhat is the application here, do you need to accept video in?21:05
azonenbergi thought this was only for generating video21:05
lekernelIOSERDES are merely shift registers + layers of flip flops21:05
azonenbergbecause for *sending* vidoe, the IOSERDES should work fine21:06
azonenbergvideo*21:06
lekernelnot in 1080p6021:06
azonenbergand at higher speed, the GTPs should be usable21:06
lekernelwon't the GTP enforce some encoding that permits clock recovery on the receiving side and is not what should be used for HDMI?21:07
azonenbergThats what i'm wondering21:07
azonenbergdoes it mandate IBM 8b10b?21:07
azonenberglike i said i've never actually used the GTPs21:07
lekerneland yes I need to receive video too21:07
azonenbergWell in that case if the gtp requires clock recovery that wont work21:07
azonenbergphase-shifted sampling may or may not, but i'm inclined to say no21:08
azonenbergthe limit is not just Fclk, it's setup/hold times too21:08
azonenbergwhich the incoming phase-shifted data will likely not respect21:08
lekernelah and yes, Lattice's SERDES are Xilinx's transceivers21:08
azonenbergCan they be used as dumb SERDES?21:09
azonenbergif they run at 3.2 Gbps they're almost certainly CML + 8b10b as used in infiniband, SATA, etc21:09
azonenbergthat seems to be turning into an industry standard for gigabit serial21:10
azonenbergHDMI is the lone holdout21:10
Action: azonenberg wonders when we'll see a GTP-compatible video standard coming out21:10
lekernelseems s21:10
lekernelo21:10
lekernelhttp://www.latticesemi.com/documents/tn1176.pdf21:10
lekernelthey have generic SERDES and 8b10b modes21:11
azonenberginteresting21:11
lekernelmaybe xilinx transceivers can work this way too... hmm21:11
lekernelbut why doesn't the xilinx dvi demo use those? hmm21:11
Action: azonenberg pulls UG38621:11
lekernelhttp://www.latticesemi.com/corporate/newscenter/newsletters/newsjanuary2011/ecp3hdmidviinterfacerefer.cfm21:12
lekernelLatticeECP3 FPGA devices to transmit and receive the TMDS signaling used by DVI and HDMI and achieving up to a full 1.65Gbps data rate in the low-cost FPGA.21:12
azonenberginteresting21:12
lekernelso, this is explicitly supported here21:12
azonenberg"The actual width of the port depends on the GTPA1_DUAL tiles INTDATAWIDTH setting (controls the width of the internal datapath), and whether or not the 8B/10B encoder is enabled."21:12
lekernelxilinx however: http://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf21:13
azonenbergSo the s6 GTP should be capable of transmitting TMDS with the GTPs21:13
lekernelonly 720p/1080i21:13
azonenbergnot sure about receiving21:13
azonenbergand that appnote is supposed to be about using the lowest end chips21:14
azonenbergthe LXT are higher end21:14
azonenberghe GTP transceiver includes an 8B/10B decoder to decode RX data without consuming21:14
azonenbergFPGA resources. The decoder includes status signals to indicate errors and incoming21:14
azonenbergcontrol sequences. If decoding is not needed, the block can be disabled to minimize latency.21:14
lekernellattice says it works for receiving too21:14
azonenbergHmm21:15
azonenbergIs it possible to do clock recovery on TMDS data?21:15
lekernelwhat a horrible UI http://www.latticesemi.com/documents/UG36.pdf21:15
azonenbergLOL21:16
azonenberganyway reading pages 150-160 of UG386 suggests it may be possible to use external clocking on the rx21:18
azonenbergnot certain yet21:18
larsclekernel: I think I've seen that demo at work today21:19
larscthat UI21:19
larscI think a colleague of mine does HDMI RX with a lattice fpga21:20
Fallenou:)21:21
lekernellarsc: at what speed?22:13
rohlekernel: bootlab exists. but its only a few persons now23:00
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