#milkymist IRC log for Sunday, 2012-08-05

wolfspraulwell, I'm a beginner01:20
wolfspraulbut as such, I don't currently understand that high vertical stack01:20
wolfspraulfrom where I am now, the physical resources, if I look up, there's first the place and route stage01:20
wolfspraulabove that, logic mapping01:20
wolfspraulabove that, logic optimization01:21
wolfspraulabove that, the verilog compiler01:21
wolfsprauland above that, things like c-to-verilog or migen01:21
wolfspraulwow01:21
wolfsprauland when the stack is somehow not powerful enough, you add more stuff to the top of it, more abstractions?01:21
wolfspraulwell then, what I work on is more like a 'libfpga' for now01:21
wolfspraulthat will allow you to write into the fpga resources, and if the api is done well it should not be too inefficient to use this api to load a design into the chip01:22
wolfspraulI will not work on connecting the traditional vertical stack to this until at least an important subset of the fpga's features work01:22
wolfsprauland then I will probably start in iverilog, reactivate the fpga targets there01:23
wpwraki think by the time you get there, you'll have a much clearer picture of what you need anyway01:26
wolfspraulI currently think one reason for the high stack is that the lower levels are closed01:27
wpwrakalso, once you bring your baby into the open, there ought to be some folks who are interested to help. there are a lot of cute algorithms waiting for a problem they can solve :)01:27
wpwrakthat may very well be the case01:27
wolfspraulI'm curious about the vivado thing, whether there is anything fundamentally new in there, or just more layers on top, with gcc/linux/arm integration etc.01:27
wpwrakfor making a "compiler", the best approach is probably to make something that can build a complete skeleton, no matter how inefficiently. then add manual overrides that guide it.01:28
wolfspraulso is vivado a repackaged ise + new things on top? or a from-scratch reimplementation of fundamental tools in the process?01:28
wolfspraulI don't know01:28
wolfspraulyeah I'm not worried about that, I really focus on the bit level and fpga physical resources01:29
wpwrakwith the whole thing open, you can collapse the stack at your leisure01:29
wolfspraulyes, that's for later01:29
wolfspraulnow I work in switches, I think there are pass transistors, tri-state buffers, and multiplexers01:29
wolfspraulhopefully that's it01:30
wpwrakalready whether to c-to-verilog or to c-to-netlist or maybe even c-to-bitstream would be entirely your/our choice01:30
wolfspraulsure just explaining my thinking, since I was torn over these things01:30
wolfspraulsuch as whether I should look at iverilog and restart the fpga target there01:30
wolfspraulbut I don't need it, it's a detour that won't help me01:30
wpwrakyeah, there are only so many things a switch can do :)01:31
wolfspraulwho knows :-)01:31
wpwrakat the beginning, you want something very simple anyway. doesn't matter how inconvenient it is.01:31
wolfspraulit's not inconvenient01:32
wolfsprauljust if you build bottom up, the need for a high vertical stack is not immediately obvious01:32
wolfspraulthat will come later when dealing with much larger designs01:32
wpwrakx = create_lut(NOR); route(x.out, y.in, sw1, sw2, ...); etc. :)01:32
wolfspraulyes01:32
wolfspraulsomething like that01:32
wpwrakwell, make that create_lut(NOR, LUT_number); :)01:33
wolfsprauland you can build the api up a little01:33
wolfspraulcreate_bunch_of_luts()01:33
wpwrakthat's already very very sophisticated :)01:33
wpwrakbut i wouldn't worry about the tall stack. chances are others will write most of that for you, if you let them :)01:34
lekernelwhat c-to-verilog does is generate a hardware implementation of a normal algorithm written in C07:47
lekernelnot manipulate the fpga/verilog level from C routines07:48
lekernelwolfspraul: looked at jbits?07:57
lekerneleg http://www-inst.eecs.berkeley.edu/~cs294-59/fa10/resources/Xilinx-history/jbits.pdf07:57
wolfspraulyes I looked at jbits09:07
wolfspraulnothing in it like all other similar projects, the closest is debit but even that is basically nothing09:07
wolfspraulthe jbits guys made their fatal mistake right on day 1 when building on top of the closed & proprietary xilinx library, no? was it that one? I studied so many I lost overview a little, but I think that was that one09:08
wolfspraulthen in the end xilinx pulled the plug under their library and that was the end of jbits, obviously09:08
wolfspraulif that was another one, sorry, then I confused them. won't look at it again now...09:09
wolfsprauldebit at least seems to have a nice crc algorithm I may end up reusing :-)09:10
wolfspraulnot that that is in any way central to the problem though09:10
wpwrak(studied so many) you really should take notes. this sort of background research is important when you have to position/defend your work.09:11
wolfspraulyes sure but I really want to get something working first09:13
wolfspraulthe majority of prior attempts in this area either gives up right away, or ends with large databases of whatever structured fpga data, and that was it. data overload, bridge collapsed...09:14
wolfspraulmy stuff may very well end like that too, and then there is no need to even document that09:14
wolfspraultoday is switch day :-)09:14
wolfsprauland tomorrow too, unfortunately. surely. and all of next week :-)09:15
wpwrakyeah, but by then you'll have forgotten the details of your background research (see above) and you'd have to do it again, which you'll find countless excuses for not doing, which in turn will make you miss opportunities to properly present your project.09:15
wpwrakalways keep in mind that you may get approached by people who'd be willing to spend not only praise but also money :)09:15
wolfspraulalso in the case of jbits, that's long long dead and history09:15
wpwrak(switch week) well, i've had worse ;-)09:16
wolfspraulI do plan to contact the recobus guys in germany, but only if I actually have something I think is worthy of their attention09:16
wolfspraulthe recobus team/effort is the most active and most advanced currently, that I'm aware of09:16
wolfspraulthey clearly are ahead of where I am, reading their papers etc. but unfortunately it's all closed, except for some binary apps they are releasing09:17
wolfspraulat least if I go back to their papers every few weeks, it slowly makes more and more sense09:17
wolfspraulso I must be on the right track :-)09:17
wolfspraultrust me werner it's too early to make a big show now09:18
wolfspraulI have nothing, just falling around09:18
wolfsprauland that after 2 months09:19
wolfspraulso let's see09:19
wolfspraulI think I will go back to the bits proper soon, after the whole modeling detour09:19
wolfspraulbits is more fun than model09:20
wpwraki'm not talking about a big show before you have something to show. that would obviously be ill-advised. but you should make sure what you learn isn't lost. and background research is an important part of that.09:20
wpwrakand 2 months is nothing ;-)09:22
lekerneljbits is a xilinx project, no?09:44
lekerneland as far as I know, it works. if you have old virtex-2's :)09:45
lekernelthat is, you can configure LUTs, route stuff, etc. and generate a programmable bitstream in the end09:45
wolfspraulthe famous 'it works'09:53
wolfspraulhow does this help us?09:53
wolfspraul1. it's abandoned for >10 yr09:53
wolfspraul2. it's based on a closed library which is officially 'retracted' and what not for ages09:53
wolfspraul3. it only "works" with ancient fpgas, where I'm sure not many people have tried this "working" status in years09:54
wolfspraul4. there is no interesting documentation whatsoever in it or around it that we could learn anything from09:54
wolfspraulso what is it good for then? I don't get it09:54
wolfspraulit's merely a distraction. the less brain resources we waste on it the better.09:55
wolfspraulI can recommend that fpga book you recommended to me a while back09:56
wolfspraulthat's a nice one09:56
wolfsprauland then the recobus project, they have good work and good papers09:56
wolfspraulthen there are some interesting bits in debit, unfortunately they stopped way too early though, imho09:57
wolfspraulafter those the quality and reusability drops a lot09:57
wolfspraulsure there are some more, like this jbits, or tarc? something with tar...09:58
wolfsprauland a few others09:58
wolfspraulbut the quality lacks there, a lot09:58
wolfsprauland some are really lousy, more like 5 page wishful thinking thesis...09:58
wolfspraulthe bottom end09:58
lekernelyour program seems to aim at the same API as jbits in the end10:08
lekernelwhich is different from c-to-verilog or logic synthesis10:09
wolfspraulyes10:10
wolfspraullowest level first10:10
lekerneldon't know why you say there's "nothing it in". it does what your program is supposed to do, only the source is closed10:10
lekernelin it10:11
wolfspraulah, yes :-)10:11
hellekinhui20:24
hellekinShit, 29C3 will be held in Hamburg. That's bad news for EHSM20:25
larscwe'll see20:32
hellekinit's kind of conflicting in the dates.20:33
lekernelhellekin: just go to EHSM *g*21:21
kristianpaul:-\22:00
kristianpaullekernel, EHSM will stream over the internet as well as CCC right?22:00
lekernelhopefully22:04
hellekinyes, and (some) CCC talks should be transmitted to EHSM too22:10
lekernelupdated the website a little http://milkymist.org/22:15
kristianpaulgot wordpress hacked?22:16
lekernelno, got simply annoyed with wordpress22:17
kristianpaulyeah, you use a lot that word :)22:17
kristianpaulpersonally, looks tooo white....22:17
kristianpauland simpler..22:17
kristianpaulwp was better :)22:19
kristianpaulahh the menu exits !22:19
kristianpaulhard to notice22:19
kristianpaulgood, web irc chat22:19
sh4rm4ah, much better22:23
kristianpaulM3 link sure call atention, but you could provide more information as not all people may want to be suscribe to ML22:24
sh4rm4the wp site was horrible22:24
sh4rm45 clicks or so until getting to the maillist archive22:24
kristianpaulwe have a pharse "sin gustos no hay disgustos" :-)22:24
kristianpaulsh4rm4: i agree on that issue that some links were hard to find..22:26
wpwrakah, very compact and austere new design. the first page may be a bit overloaded ... you hardly notice the prod/tech/comm links.23:28
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