#milkymist IRC log for Wednesday, 2012-07-25

kristianpaulhum that migen re-use for just top and csr generation  dont look bad01:36
kristianpauljust to get used to the pythonic way of writing the top "config file"01:36
xiangfuazonenberg, Hi06:40
azonenbergwhats up?06:40
xiangfuazonenberg, I try to make a tiny slx9 board for learn. the first thing I need to is:  power-on the chip and make jtag detect the chip.06:41
azonenbergxiangfu: Sorry, cant talk tech now - it's 3AM and i'm getting ready to go to sleep06:41
xiangfuazonenberg, sure.06:41
azonenbergi'll be hanging out with $GF tomorrow but if you ping me in the early evening my time (EDT) i'll see what i can do06:42
xiangfuazonenberg, good night. thanks.06:42
xiangfuazonenberg, I learn base on your slx9-azonenberg-devboards , BTW. :-)06:43
azonenbergGlad to hear it's getting used06:44
azonenbergI assembled one of the boards and it works fine06:44
azonenbergwill do the other two soon06:44
azonenbergThe one mistake in the original design was that R8 (I think? the 10k pulldown on one of the mode pins) should have been 10 ohms, or any small value06:44
azonenbergi forgot the chip has an on-die pullup and you have to pull down strongly enough to override that06:44
azonenbergNot a layout change, just a BOM tweak06:45
xiangfuI read that. you rock and fast. I am working very hard try to catch up with you. :-D like make a board in one day.06:45
xiangfuI finished soldering my first QFP 144 by hand.06:46
xiangfuazonenberg, one simple question. there are like 5 VCCINT/AUX/_O pins. for power-on the chip. I only needs connect one GND, one VCCINT, one VCCAUX and one VCC_O_2 is enough, right? no needs connect all them06:54
Hawk777xiangfu: in most cases they will all be connected together inside the package, *but* you will have issues if you don't connect all of them because the inductance of the pins on the chip will be higher than expected so there can be more voltage drop during switching inside the chip07:13
Hawk777I believe you can safely leave out the VCCOs for I/O banks you're not using at all, though.07:13
xiangfuHawk777, from the datesheet. if I understand right. I have to connect VCCO_2  for using jtag07:14
xiangfuHawk777, thanks for reply07:14
Hawk777probably, if that's the I/O bank the JTAG pins ar ein07:14
Hawk777I use SLX9 myself in a project, but I haven't done JTAG and I've always just connected VCCINT to 1.2 and every single other power supply pin to 3.307:15
xiangfumy side is ever simple. I just want make the jtag detect the chip correct. so I connect VCCINT to 1.2, VCCAUX to 2.5 and VCC_O_2 to 3.3.07:17
xiangfuthen connect those 4 jtag pins.07:17
Hawk777that'll probably work07:17
xiangfumaybe I try to connect VCCAUX to 3.3? like you do?07:18
Hawk777did you try your idea and it didn't work?07:18
xiangfuyes. I tried. the board is like: 'http://downloads.qi-hardware.com/people/xiangfu/tmp/IMG_0609.JPG'07:18
xiangfunow the pins are connected. when I run 'detect', I always get ' TDO seems to be stuck at 1'07:19
Hawk777ah, just a big breakout07:19
Hawk777stuck at 1 is kind of weird07:19
Hawk777if it's not powered I would have expected stuck at 007:19
Hawk777unless there JTAG host has a pull-up resistor or osmething07:20
Hawk777anyway I just use 3.3 VCCAUX because then I don't need a 2.5 V regulator on my board07:20
Hawk777"For configuration, Spartan-6 devices require power on the VCCO_2, VCCAUX, and VCCINT pins."07:21
Hawk777So there's your answer: none of the other I/O banks should be needed.07:21
Hawk777Maybe you want to try providing power to all the VCCAUX and VCCINT pins instead of just one of each?07:21
xiangfuHawk777, I tried 3 of them. now. I connect all them ....07:24
xiangfuI must do something wrong. it still give 'stuck at 1'07:26
Hawk777do you have any way to look at the JTAG pins, maybe a scope?07:26
xiangfuI have a usb hantek scope. but I dont' have much experience on scope.07:29
Hawk777ah, well the idea would be just to look at the TDI, TDO, TMS, and TCK lines to see if there's any activity at all07:29
Hawk777also, that board you sent the photo of07:30
Hawk777did you make that yourself, or buy it?07:30
Hawk777(soldering the FPGA)07:30
xiangfuI soldering them by myself. I bought this premake PCB.07:33
Hawk777because maybe there's a solder bridge between two pins and one of them is a JTAG pin?07:34
Hawk777that would explain a stuck pin07:34
xiangfuI check the 4 jtag pins many time. I am sure they are good.07:34
Hawk777Ah, it's not something about crossing wires is it? Haven't used JTAG so I don't know, but maybe TDI on the FPGA has to go to TDO on the host and vice versa or something like that?07:35
Hawk777Or maybe if you did that, it's not supposed to?07:35
xiangfuHawk777, crossing wires. no. I have double check them.07:41
xiangfuHawk777, maybe I try to soldering another board.07:41
Hawk777you could07:41
Hawk777maybe the FPGA was damaged at some point07:41
xiangfunot sure if I broken this chip when I soldering this one.07:41
xiangfuHawk777, yes. soldering another one in next hour.07:46
Hawk777heh, yeah :/07:47
azonenbergxiangfu: you have to connect all of the vccint and vccaux for the chip to work reliably08:19
azonenbergvcco_2 is needed for jtag08:19
azonenbergcheck the datasheet, it may be possible to leave off vcco for banks you arent using08:19
azonenbergyou should probably ground it rather than leaving it floating08:19
azonenbergwhich wont be any harder to route, probably, than hooking it up properly08:19
xiangfuazonenberg, thanks.08:20
sb0iirc the FPGA only starts to configure after all VCCO's have reached some level08:20
azonenbergI've always hooked them all up08:21
azonenbergits doable on 2 layers08:21
azonenbergfor a tq14408:21
xiangfuall VCCO's?08:21
xiangfuok. I will try connect all VCCO08:21
azonenberglook at my board08:21
azonenbergi had two concentric rings on one layer and a plane on the other08:21
azonenbergi even got in nice decoupling08:21
azonenbergwhile routing about half of the IOs to headers and useful stuff08:22
azonenbergi could have routed the other IOs too but not without making the board larger08:22
Fallenourejon let him complain (about price increase) :)18:16
Fallenouand maybe he is not wrong, maybe a prince increase communicate can somehow have positive outputs ^^18:17
FallenouI don't know how :p18:17
Fallenoubut sometime relationship between price and sells is tricky18:17
Fallenouthat may send a signal to some company which could start paying attention to Milkymist  / Ben18:18
mwalleFallenou: for debug purposes, eg for the debug monitor18:55
mwalleFallenou: i guess it isnt hard to read back the value of the internal RAM for a given VADDR18:55
mwalleFallenou: wpwrak: do we need the protection bits for both user and kernel access?18:56
Fallenouwell it may need to use a dual ported blockram18:59
Fallenouor it may need to disable tlb18:59
mwalleFallenou: isnt it as easy as return dtlb_read_data on read on PADDR?19:01
Fallenouwell you need to feed "address" signal of blockram with your VADDR19:02
Fallenouin this precise condition (rcsr on PADDR)19:02
mwalleFallenou: yeah, you write VADDR and read PADDR19:02
Fallenouwhile you are fetching other instructions19:02
Fallenouwhich means you need in parallel to have address_a in address signal of blockram19:03
mwalleassume MMU is turned of, because its only for debugging ;)19:03
Fallenouto lookup address_f (fetch)19:03
Fallenouif mmu is turned off, then it's easier of course :)19:03
mwallemh ok, i see, the problem is that the tlb is used by the instruction unit and the cache while a user may try to access it19:04
mwalleFallenou: well in that case, we may drop this ;19:05
mwalleits just a nice to have19:08
mwalleif you put a mux in before the dtlb_data_read_address, there may be other side effects if you switch the mmu on and off, i guess19:09
Fallenoumwalle: that's what I fear indeed19:28
Fallenoumaybe I will try when tlb will be rock solid stable19:28
Fallenoubut for now, even with the very limited feature set I have right now, it still has bugs19:28
Fallenouso first, I improve stability :)19:28
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