#milkymist IRC log for Sunday, 2012-07-22

GitHub37[linux-milkymist] larsclausen pushed 1000 new commits to master: http://git.io/R-DlUg18:39
GitHub37[linux-milkymist/master] Btrfs: fix locking in btrfs_destroy_delayed_refs - Josef Bacik18:39
GitHub37[linux-milkymist/master] Btrfs: wake up transaction waiters when aborting a transaction - Josef Bacik18:39
GitHub37[linux-milkymist/master] Btrfs: abort the transaction if the commit fails - Josef Bacik18:39
Fallenouwow 1000 commits, you are committing quite fast ;)18:42
larsctook half an hour to even push those commits18:46
Fallenouahah18:49
Fallenouyou can't even visualize them using the github link provided on irc18:49
Fallenouerror 500 :)18:49
Fallenoularsc: did you try to boot it up ?18:51
FallenouI tried a few days ago I got nothing in my uart console18:51
larscFallenou: yes18:54
larscI get a shell18:54
Fallenouoh, weird18:54
larscyou need to pass 'console=ttyS0' to the kernel command line18:54
Fallenouoh right :)18:54
FallenouI was not using any cmdline18:55
larscunfortunately something in libc's execvp is broken and I can't spawn any other process19:12
Fallenouarg19:23
mwalleFallenou: i just need the VADDR for invalidating, right?19:46
Fallenouyes19:49
Fallenouvaddr only is enough19:49
Fallenoupfn(vaddr)19:49
Fallenouyou can set the page offset bits to whatever you want, they will get ignored19:50
Fallenoudoes someone have another opinion on the 4 kB / 8 kB page size ?19:50
Fallenouor even 16 kB :)19:51
larschm the bug seems to be a compiler bug, or whatever, the mmap implementation in libc got doesn't set the signal numner :/20:07
larscmwalle: do you remember the problem we had with the register write to r8 being optimized out? Didn't we fix that?20:07
larscwith this crazy hack in the kernel it works:20:23
larsc+       ori r3, r0, 13520:23
larsc+       bne r8, r3, 1f20:23
larsc+       ori r3, r0, 409520:23
larsc+       bne r2, r3, 1f20:23
larsc+       mvi r8, 22220:23
larsc+20:23
mwallelarsc: na that was discussed on gcc ml20:24
mwallebut was never fixed / seen as a problem20:24
larscbut I think we had a workaround for it20:25
mwallelarsc: yeah20:26
mwallebut i dont remember20:26
mwallesome syscalls didnt work20:27
larschttps://github.com/milkymist/uclibc-lm32/commit/df1075d1adc5dbc53e7746b0d80ade0b78b4deeb20:27
larsci guess that's the one20:27
larscyea, that's it20:28
mwallehttp://gcc.gnu.org/ml/gcc/2011-08/msg00023.html20:28
mwallethat was the ML thread20:28
mwalleFallenou: i guess we can test it and make some measurements and then decide whats the best page size20:29
Fallenouyeah I guess20:35
larscyeay, with that fix it works fine again20:39
mwalleFallenou: how can i distingish between and itlb and dtlb miss in the exception?20:41
GitHub146[milkymist-mmu] fallen pushed 1 new commit to mmu: http://git.io/3E7MZg20:43
GitHub146[milkymist-mmu/mmu] Add ITLB and PSW CSR register and a little bit of refactoring - Yann Sionneau20:43
Fallenoumwalle: 2 different exception vectors20:43
Fallenousee in the commit I just pushed, in crt0.S20:44
mwalleFallenou: would it be possible to put them into one and make a cause register?20:47
mwallebecause once we have some more functionalities like protection bits, the have to be a cause register anyway20:48
Fallenouthe cause bits would need to be saved upon exception20:50
Fallenouso it will end up in PSW I guess ?20:51
mwalleFallenou: mh? it would be the same handling as the BADADDR register20:52
mwalledunno how you named it TLBMA ?20:52
mwalleset CAUSE + BADADDR, raise exception20:54
Fallenouin theory another tlb miss should not happen while in tlb miss handler20:55
Fallenouso I guess there is no point in saving CAUSE+BADADDR upon exception like ITLBE is saved in EITLBE20:55
Fallenouright ?20:55
mwalleFallenou: once there is an miss exceptions both translations are disabled, so there can't be any more TLB miss exceptions20:56
Fallenouright -_-20:57
Action: Fallenou tired20:57
mwalleFallenou: if theres a miss while loading 0x1004, do i get the BADADDR 0x1004 or 0x1004 & PAGE_MASK == 0x1000 ?21:06
Fallenouyou get the whole address21:07
mwalleFallenou: fine :)21:07
Fallenouitlb is better now but those last bugs are really annoying21:07
Fallenoureally a pain21:08
mwallehehe ;)21:08
Fallenoucrazy, I just add a new function in BIOS prompt (itlbi to flush whole ITLB)21:15
Fallenouand now I run itlbtest , which has NOTHING to do with the new bios prompt function21:15
Fallenouand now instead of behaving nicely, I got a storm of exceptions21:16
FallenouEA is set to the address of the exception handler and it goes in infinite loop of exception handling21:16
Fallenouis my stack smashed or what ?21:16
Fallenouam I going to hardcode in the verilog code "if (pc != 0x4400120) ea <= pc" ? :)21:20
FallenouI see, the joke is not funny :p21:27
mwallejust pushed the qemu repo21:57
mwallehttps://github.com/mwalle/qemu/tree/mmu21:57
mwallestill needs some more tests (eg ITLB isn't covered at all), tlb miss handler exception is wrong, USR bit not implemented yet21:58
mwalleFallenou: wpwrak: lekernel: so what do you think, one or two exception handlers?21:59
FallenouI guess it's cleaner to only have one exception handler for all MMU related stuff (*tlb miss, protection fault (read/write/execute)) ?22:02
Fallenoudunno honestly22:02
FallenouI did two separate because in my head dtlb and itlb are really two different things22:03
Fallenoubut both could be handled in the same exception handler actually22:03
wpwrakmwalle: i guess we should try either and benchmark.22:03
Fallenoua lot of benchmarks :)22:05
Fallenouwell I don't know if there would be differences22:05
Fallenouthat's just an extra "if" in the handler22:05
wpwrakyou could of course have a "set TLB that caused the last exception" operation :)22:10
wpwrakand i'd separate TLB miss from permission or page fault. TLB miss can be a very streamlined piece of code and should run very often in comparison to the others.22:11
Fallenouthat would not be hard to implement a bit in PSW that would be 0 if last TLB miss was DTLB, and 1 for ITLB22:11
Fallenousomething like that22:11
Fallenouwpwrak: ok why not22:11
mwalleFallenou: use an own register for the cause, not the psw, because thats the processor state22:13
Fallenoummu state ?22:13
Fallenoucreate another extra CSR ?22:13
mwalleFallenou: or use TLBCTRL for reading22:14
Fallenouoh, right22:14
mwalleFallenou: in mips its named BADADDR and CAUSE register22:15
mwallewpwrak: maybe we should actually write a performant tlb miss handler and see what the hw can do to optimize it22:16
mwallebut not now, i'm going to bed ;)22:16
Fallenouthe same here22:16
FallenouI can't think straight anymore22:16
Fallenouworked on itlb at least 15 hours this week-end :)22:16
Fallenougn8!22:17
mwallegn822:17
Fallenouoh, and thanks for the qemu commits !22:17
mwallenp, i guess the interesting part is the test_mmu.S22:18
mwalleinn tests/tcg/lm32/22:18
Fallenou:)22:18
Fallenousure22:19
wpwrakmwalle: yeah, a reference TLB miss handler would be a good thing to have. not sure how close to the real thing you can get without actually writing the real thing, though.22:21
wpwrak(or making the difference trivial)22:21
Fallenoumaybe you can just think of what you'd like the hardware to provide (informations in registers etc)22:22
Fallenoufor the software to be as straight forward to write22:22
Fallenouand as fast and efficient as possible22:22
Fallenouwhile writting the C-like code, I think the idea of what you need and how you would need it to be efficient would come to mind22:23
wpwrakhmm ... uint32_t **ptd = PAGE_TABLE_DIRECTORY_ADDR; addr = VA_REG; /* forgot the name */ uint32_t *pt = ptd[addr >> 22]; if (!pt) goto no_page_fault; uint32_t pte = pt[(addr >> 12) & 0x1023]; if (!pte) goto no_page_fault; PA_REG = pte; CMD_REG = CMD_WRITE_TLB; return;22:35
wpwrakall  if (x)  would be  if (unlikely(x))  (not sure this matters in this case, though)22:36
Fallenouwo wo, please, post this in a pastebin, or a piratepad to allow other to modify :p22:37
Fallenouit's unreadable on 1 line22:37
Fallenouhttp://piratepad.net22:37
wpwrakso .. 1) the register that holds the VA that caused the miss should be the same as the one that holds the VA for updating the TLB. 2) the code could be even shorter if a write to the PA register implicitly triggers a TLB update22:38
wpwraki'll post to the list22:38
Fallenouok great :)22:38
Fallenou1) it's the case22:38
Fallenou2) very good idea !22:38
Fallenouhttp://piratepad.net/RSE6AWxIIa < the piratepad of when I started to think about the mmu22:40
Fallenoua lot of what's written there is out of date22:40
Fallenoubut I just added a TODO at the bottom22:40
Fallenoufeel free to write things in it22:40
Fallenou(and notify me when you do :p)22:40
Fallenougoing to bed, gn8!22:42
wpwraki'll just stick with mail. don't like to scatter discussions over a dozen different media ;-)22:45
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