| wolfspra1l | lekernel: the other day you mentioned that icarus verilog removed options to synthesize verilog to netlists because it didn't work well | 01:16 |
|---|---|---|
| wolfspra1l | but reading the iverilog documentation they do mention an 'fpga' target that seems to output edif netlists etc. | 01:16 |
| wolfspra1l | isn't that the same thing? | 01:16 |
| wolfspra1l | what did they remove or give up on? | 01:16 |
| wolfspra1l | I'm looking at iverilog 0.9.20111101 | 01:17 |
| azonenberg | wolfspra1l: what can you do with a verilog tool that doesnt synthesize? | 01:50 |
| azonenberg | simulate only? | 01:50 |
| wolfspra1l | if I knew I wouldn't ask :-) | 01:53 |
| wolfspra1l | "the currently supported targets are vvp for simultion, and fpga for synthesis" | 01:53 |
| wolfspra1l | "-S Synthesize" | 01:54 |
| wolfspra1l | "fpga This is a synthesis target that supports a variety of fpga devices, mostly by EDIF format output. ... implies the synthesis -S flag" | 01:54 |
| wolfspra1l | and so on | 01:54 |
| wolfspra1l | what does this mean? | 01:54 |
| wolfspra1l | sebastien said something was dropped, I'm trying to ping his brain before continuing to read on... | 01:55 |
| azonenberg | yeah, i'm not sure | 01:55 |
| azonenberg | i havent looked that far up the stack yet | 01:55 |
| azonenberg | my first-run lx9 boards are at the fab now btw | 01:55 |
| wolfspra1l | from very superficially looking at that iverilog info page, there seems to be some 'synthesis' 'fpga' or 'edit' support. but I don't know exactly what it means or what I should expect. | 01:55 |
| wolfspra1l | if nobody can tell me, I shall find out by myself :) | 01:56 |
| azonenberg | EDIF = electronic device interchange format | 01:56 |
| wolfspra1l | sure | 01:56 |
| azonenberg | its a device-independent RTL netlist | 01:56 |
| azonenberg | that then has to be mapped into technology-dependent stuff and PAR'd | 01:56 |
| wolfspra1l | seems pretty much dead, from an industry perspective, for 10+ years | 01:56 |
| azonenberg | Why do you say that | 01:56 |
| azonenberg | what do you use now? | 01:56 |
| wolfspra1l | but maybe that's good because it is just sufficient and complete for what it tries to achieve | 01:56 |
| wolfspra1l | because that's what wikipedia is saying | 01:56 |
| azonenberg | i thought edif was the only way to exchange RTL other than source code | 01:56 |
| azonenberg | link? | 01:56 |
| wolfspra1l | it may well be | 01:57 |
| wolfspra1l | and maybe that's a sign of quality! | 01:57 |
| wolfspra1l | I am trying to get some qualified statements from people who are in this longer than me | 01:57 |
| azonenberg | i see | 01:57 |
| azonenberg | i've only been doing FPGA stuff for a year myself lol | 01:57 |
| wolfspra1l | "since the release of EDIF 4, the entire EDIF standards org has essentially dissolved. There have been no... most individuals have moved on to other companies or efforts. the newsletter was abandoned, the user's group no longer holds yearly meetings" | 01:59 |
| wolfspra1l | I just shorten all that to 'dead' | 01:59 |
| wolfspra1l | which may not be bad! | 01:59 |
| wolfspra1l | maybe it's stable and achieves what it was meant for | 01:59 |
| azonenberg | Yeah | 01:59 |
| wolfspra1l | http://en.wikipedia.org/wiki/EDIF | 01:59 |
| azonenberg | to me, dead means no longer in active use, or being phased out | 01:59 |
| azonenberg | vs stable and mature | 02:00 |
| wolfspra1l | but I am sure from a corporate perspective where everything is about 'growth' and new features etc. - nobody will look at edif anymore | 02:00 |
| Action: azonenberg hates that | 02:00 | |
| wolfspra1l | exactly, it may not matter to us | 02:00 |
| azonenberg | the goal of a company shouldnt be to grow | 02:00 |
| wolfspra1l | logic or math or physics doesn't change like that | 02:00 |
| azonenberg | it should be to produce a product | 02:00 |
| azonenberg | looking on wiki under EDA file formats | 02:01 |
| azonenberg | they have CIF, GDS, LXF for masks | 02:01 |
| azonenberg | gerber for PCBs and (occasionally) IC masks | 02:01 |
| azonenberg | DXF | 02:02 |
| azonenberg | OASIS also for masks | 02:02 |
| azonenberg | but EDIF seems the only netlist format | 02:02 |
| wolfspra1l | the main thing I try to find out now is something that gets me from verilog to basic gates and netlist | 02:04 |
| wolfspra1l | first for small test circuits, and later also for the full milkymist soc | 02:04 |
| wolfspra1l | given what the iverilog documentation says, I will try a bit there | 02:04 |
| kristianpaul | wolfspra1l: perhaps this lekernel meant http://volodya-project.sourceforge.net/tgt-edif.php ? | 02:45 |
| wolfspra1l | wow that is old :-) | 03:43 |
| wolfspra1l | I will start with whatever is in iverilog today, see what that produces | 03:44 |
| wolfspraul | that was an easy answer to myself - the fpga target was removed in the iverilog 0.9 release | 07:58 |
| wolfspraul | there used to be a xnf (xilinx netlist) target which was removed after 0.8, then 'fpga' was removed after 0.9 and vhdl was added. and most recently a new 'gnu pcb' target was added. | 08:00 |
| wolfspraul | ah, http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9 | 08:04 |
| wolfspraul | here they say synthesis was broken in 0.9 but they will try to bring it back in a future release, until then 0.8 should be used for synthesis | 08:05 |
| lekernel | they said that years ago... | 11:36 |
| GitHub142 | [flickernoise] xiangfu created wireless (+1 new commit): http://git.io/LE5QJQ | 13:46 |
| GitHub142 | [flickernoise/wireless] Add wireless (wireless over OpenWrt router) configure code - Xiangfu | 13:46 |
| lekernel | another reason for switching to lua :) | 14:02 |
| xiangfu | :-), I already started learn LUA. | 14:03 |
| xiangfu | here is my first lua code: http://projects.qi-hardware.com/index.php/p/openwrt-packages/source/tree/master/milkymist-TLWR703/files/opt | 14:04 |
| Hodapp | Lua is pretty awesome. | 14:04 |
| Hodapp | it is one of the best combinations of power and simplicity that I've seen in a design. | 14:04 |
| xiangfu | another reason for switching to lua :) | 14:05 |
| kristianpaul | :) | 14:05 |
| Hodapp | it's astonishing though how the C++ folks at work couldn't figure out how to use Lua properly such that Lua's Lua-ness actually helped them. | 14:06 |
| Hodapp | instead they took the intersection of Lua and C++ and said "LUA SUCKS!" | 14:08 |
| lekernel | xiangfu: oh, great | 14:08 |
| kristianpaul | perhpas lua over rtems and re-use drivers... cause stadalone very limited multitasking | 14:09 |
| lekernel | I think things like openwrt configuration scripts are much better handled with little lua scripts than hardcoded in the C code | 14:09 |
| kristianpaul | oh sure | 14:10 |
| Hodapp | lekernel: yes, and in many cases better than having another file format that the code is parsing | 14:10 |
| lekernel | kristianpaul: I don't see an intractable multitasking problem. you can relinquish the CPU to other tasks during network I/O quite easily even with a baremetal app. | 14:11 |
| kristianpaul | yes i can, but i still wonder how efficint, let said you need to support a UI/Eth/USB/UART/TMU | 14:13 |
| kristianpaul | well... i hope i'm wrong at all | 14:13 |
| kristianpaul | is this issues is solved, imagine the news, Lua becomes the first scripting and operating system it self :) | 14:16 |
| Hodapp | isn't that kinda what eLua is? | 14:16 |
| lekernel | yup | 14:16 |
| wpwrak | Hodapp: add C++ to anything, even in homeopathic doses, and it has little hope not to suck :) | 14:17 |
| lekernel | which I'm not using because I want to play with interrupt priority levels to implement realtime tasks like rendering | 14:17 |
| lekernel | and I also like the clang-based build system common with the BIOS | 14:18 |
| lekernel | wpwrak: this is actually quite a shame, I was looking at anti grain geometry the other day | 14:19 |
| lekernel | http://www.antigrain.com/ | 14:19 |
| lekernel | which looks pretty cool... but c++ | 14:19 |
| lekernel | there's also libcairo, and the option of hacking the freetype rasterizer... both I haven't tried yet... | 14:20 |
| kristianpaul | Hodapp: ah, forgot said lua ansi c upstream :) | 14:22 |
| Hodapp | wpwrak: We're using SWIG + Lua + C++ in this project, so things are kind of a mess. | 14:29 |
| wpwrak | lekernel: sometimes, you can wrap something C++ in C. it's not supposed to be portable (because of they way C++ does intializations), but i've seen it work at least once. (using CGAL with my C code). of course, you still get ridiculous compile times for the C++ wrapper ... | 14:29 |
| Hodapp | Lua can make things so much cleaner and more elegant but instead it's just been a mess | 14:30 |
| wpwrak | Hodapp: i hope the project's dress code also includes a hair shirt to be work while programming :) | 14:30 |
| wpwrak | s/work/worn/ | 14:31 |
| Hodapp | well, it had the benefit of teaching me Lua, and I'm the one who embedded it into the application in the first place as an experiment | 14:31 |
| wpwrak | ah, the rebel :) | 14:31 |
| Hodapp | so I did at least get to see how clean it has the potential to be | 14:31 |
| Hodapp | and how wonderfully easy it is to embed | 14:31 |
| wpwrak | now, is it better to have seen purity and then lost it (to C++) or to never have known purity ? ;-) | 14:41 |
| hellekin | https://github.com/milkymist/board-m1 does not have a license... Would that be GPLv3+ or GFDL? | 15:55 |
| hellekin | /win 3 | 15:58 |
| hellekin | oops | 15:58 |
| lekernel | hellekin: cc by sa I think | 16:18 |
| hellekin | anything worng with GFDL? | 16:23 |
| hellekin | wrong | 16:23 |
| --- Thu Jul 5 2012 | 00:00 | |
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