#milkymist IRC log for Wednesday, 2012-07-04

wolfspra1llekernel: the other day you mentioned that icarus verilog removed options to synthesize verilog to netlists because it didn't work well01:16
wolfspra1lbut reading the iverilog documentation they do mention an 'fpga' target that seems to output edif netlists etc.01:16
wolfspra1lisn't that the same thing?01:16
wolfspra1lwhat did they remove or give up on?01:16
wolfspra1lI'm looking at iverilog 0.9.2011110101:17
azonenbergwolfspra1l: what can you do with a verilog tool that doesnt synthesize?01:50
azonenbergsimulate only?01:50
wolfspra1lif I knew I wouldn't ask :-)01:53
wolfspra1l"the currently supported targets are vvp for simultion, and fpga for synthesis"01:53
wolfspra1l"-S Synthesize"01:54
wolfspra1l"fpga This is a synthesis target that supports a variety of fpga devices, mostly by EDIF format output. ... implies the synthesis -S flag"01:54
wolfspra1land so on01:54
wolfspra1lwhat does this mean?01:54
wolfspra1lsebastien said something was dropped, I'm trying to ping his brain before continuing to read on...01:55
azonenbergyeah, i'm not sure01:55
azonenbergi havent looked that far up the stack yet01:55
azonenbergmy first-run lx9 boards are at the fab now btw01:55
wolfspra1lfrom very superficially looking at that iverilog info page, there seems to be some 'synthesis' 'fpga' or 'edit' support. but I don't know exactly what it means or what I should expect.01:55
wolfspra1lif nobody can tell me, I shall find out by myself :)01:56
azonenbergEDIF = electronic device interchange format01:56
azonenbergits a device-independent RTL netlist01:56
azonenbergthat then has to be mapped into technology-dependent stuff and PAR'd01:56
wolfspra1lseems pretty much dead, from an industry perspective, for 10+ years01:56
azonenbergWhy do you say that01:56
azonenbergwhat do you use now?01:56
wolfspra1lbut maybe that's good because it is just sufficient and complete for what it tries to achieve01:56
wolfspra1lbecause that's what wikipedia is saying01:56
azonenbergi thought edif was the only way to exchange RTL other than source code01:56
wolfspra1lit may well be01:57
wolfspra1land maybe that's a sign of quality!01:57
wolfspra1lI am trying to get some qualified statements from people who are in this longer than me01:57
azonenbergi see01:57
azonenbergi've only been doing FPGA stuff for a year myself lol01:57
wolfspra1l"since the release of EDIF 4, the entire EDIF standards org has essentially dissolved. There have been no... most individuals have moved on to other companies or efforts. the newsletter was abandoned, the user's group no longer holds yearly meetings"01:59
wolfspra1lI just shorten all that to 'dead'01:59
wolfspra1lwhich may not be bad!01:59
wolfspra1lmaybe it's stable and achieves what it was meant for01:59
azonenbergto me, dead means no longer in active use, or being phased out01:59
azonenbergvs stable and mature02:00
wolfspra1lbut I am sure from a corporate perspective where everything is about 'growth' and new features etc. - nobody will look at edif anymore02:00
Action: azonenberg hates that02:00
wolfspra1lexactly, it may not matter to us02:00
azonenbergthe goal of a company shouldnt be to grow02:00
wolfspra1llogic or math or physics doesn't change like that02:00
azonenbergit should be to produce a product02:00
azonenberglooking on wiki under EDA file formats02:01
azonenbergthey have CIF, GDS, LXF for masks02:01
azonenberggerber for PCBs and (occasionally) IC masks02:01
azonenbergOASIS also for masks02:02
azonenbergbut EDIF seems the only netlist format02:02
wolfspra1lthe main thing I try to find out now is something that gets me from verilog to basic gates and netlist02:04
wolfspra1lfirst for small test circuits, and later also for the full milkymist soc02:04
wolfspra1lgiven what the iverilog documentation says, I will try a bit there02:04
kristianpaulwolfspra1l: perhaps this lekernel meant http://volodya-project.sourceforge.net/tgt-edif.php ?02:45
wolfspra1lwow that is old :-)03:43
wolfspra1lI will start with whatever is in iverilog today, see what that produces03:44
wolfspraulthat was an easy answer to myself - the fpga target was removed in the iverilog 0.9 release07:58
wolfspraulthere used to be a xnf (xilinx netlist) target which was removed after 0.8, then 'fpga' was removed after 0.9 and vhdl was added. and most recently a new 'gnu pcb' target was added.08:00
wolfspraulah, http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_908:04
wolfspraulhere they say synthesis was broken in 0.9 but they will try to bring it back in a future release, until then 0.8 should be used for synthesis08:05
lekernelthey said that years ago...11:36
GitHub142[flickernoise] xiangfu created wireless (+1 new commit): http://git.io/LE5QJQ13:46
GitHub142[flickernoise/wireless] Add wireless (wireless over OpenWrt router) configure code - Xiangfu13:46
lekernelanother reason for switching to lua :)14:02
xiangfu:-), I already started learn LUA.14:03
xiangfuhere is my first lua code: http://projects.qi-hardware.com/index.php/p/openwrt-packages/source/tree/master/milkymist-TLWR703/files/opt14:04
HodappLua is pretty awesome.14:04
Hodappit is one of the best combinations of power and simplicity that I've seen in a design.14:04
xiangfuanother reason for switching to lua :)14:05
Hodappit's astonishing though how the C++ folks at work couldn't figure out how to use Lua properly such that Lua's Lua-ness actually helped them.14:06
Hodappinstead they took the intersection of Lua and C++ and said "LUA SUCKS!"14:08
lekernelxiangfu: oh, great14:08
kristianpaulperhpas lua over rtems and re-use drivers... cause stadalone very limited multitasking14:09
lekernelI think things like openwrt configuration scripts are much better handled with little lua scripts than hardcoded in the C code14:09
kristianpauloh sure14:10
Hodapplekernel: yes, and in many cases better than having another file format that the code is parsing14:10
lekernelkristianpaul: I don't see an intractable multitasking problem. you can relinquish the CPU to other tasks during network I/O quite easily even with a baremetal app.14:11
kristianpaulyes i can, but i still wonder how efficint, let said you need to support a UI/Eth/USB/UART/TMU14:13
kristianpaulwell... i hope i'm wrong at all14:13
kristianpaulis this issues is solved, imagine the news, Lua becomes the first scripting and operating system it self :)14:16
Hodappisn't that kinda what eLua is?14:16
wpwrakHodapp: add C++ to anything, even in homeopathic doses, and it has little hope not to suck :)14:17
lekernelwhich I'm not using because I want to play with interrupt priority levels to implement realtime tasks like rendering14:17
lekerneland I also like the clang-based build system common with the BIOS14:18
lekernelwpwrak: this is actually quite a shame, I was looking at anti grain geometry the other day14:19
lekernelwhich looks pretty cool... but c++14:19
lekernelthere's also libcairo, and the option of hacking the freetype rasterizer... both I haven't tried yet...14:20
kristianpaulHodapp: ah, forgot said lua ansi c upstream :)14:22
Hodappwpwrak: We're using SWIG + Lua + C++ in this project, so things are kind of a mess.14:29
wpwraklekernel: sometimes, you can wrap something C++ in C. it's not supposed to be portable (because of they way C++ does intializations), but i've seen it work at least once. (using CGAL with my C code). of course, you still get ridiculous compile times for the C++ wrapper ...14:29
HodappLua can make things so much cleaner and more elegant but instead it's just been a mess14:30
wpwrakHodapp: i hope the project's dress code also includes a hair shirt to be work while programming :)14:30
Hodappwell, it had the benefit of teaching me Lua, and I'm the one who embedded it into the application in the first place as an experiment14:31
wpwrakah, the rebel :)14:31
Hodappso I did at least get to see how clean it has the potential to be14:31
Hodappand how wonderfully easy it is to embed14:31
wpwraknow, is it better to have seen purity and then lost it (to C++) or to never have known purity ? ;-)14:41
hellekinhttps://github.com/milkymist/board-m1 does not have a license... Would that be GPLv3+ or GFDL?15:55
hellekin  /win 315:58
lekernelhellekin: cc by sa I think16:18
hellekinanything worng with GFDL?16:23
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