#milkymist IRC log for Friday, 2012-06-29

azonenbergwolfspraul: just committed a final BOm00:05
wolfspraulyou are fast00:05
azonenberg$55.81 including PCB and all optional components00:05
wolfspraulI need to get my morning coffee00:05
azonenbergbefore bulk discount00:05
azonenbergiow, assuming you pay 17 cents for every single decoupling cap00:05
azonenberg$40.40 of that is the required stuff, the rest is optional accessories00:06
azonenbergWhoops, forgot to tab-to-space00:06
azonenbergfixed00:07
azonenbergwolfspraul: let me know when you've had a chance to look over the design in some detail00:12
azonenbergi'm probably going to add an oscilloscope ground clip and a couple of probe pads with silkscreened labels on interesting signals00:13
azonenbergbut other than that it's finished00:13
wolfspraulI'm super focused on fpgatools hacking right now, but I will ask Adam whether he has some time to review the board00:14
azonenbergOk, let me phrase this a little differently00:14
wolfspraulor when I need a little rest from coding, I will peek over it too, of course00:14
azonenbergI'm going to send the design out for first-run prototype fab tonight or tomorrow so any comments received after that point will have to wait for rev 0.200:15
wolfspraulunderstood00:15
lekernel_http://gcc.gnu.org/viewcvs/trunk/gcc/config/lm32/lm32.c?r1=187199&r2=188918&diff_format=h ahem...08:55
lekernel_someone fixed it though08:55
Jiajust this?08:56
lekernel_crtl->is_leaf!08:57
Action: Jia is git pulling08:58
lekernelsvn xD09:00
lekernelfunny, they had to trash their repository 3 months ago and restart from scratch. this reminds me of the times when milkymist was still using svn...09:01
wpwrakhmm, absolute libray name paths09:03
Jia2012-06-29  Nick Clifton  <nickc@redhat.com>       config/lm32/lm32.c (lm32_compute_frame_size): Fix typo.09:03
Jiait just a typo... ???09:03
lekernel"!current_function_is_leaf" turning into "crtl->is_leaf!" does look like it, yes09:04
wpwrak(at least) one unannotated component (P?). ERC passes after auto-annotation.09:05
wpwrakquite large series resistors for the LEDs (470 Ohm). that's about 2-3 mA09:08
wpwrakazonenberg: why is SPI_SCK on a voltage divider ? (R4/R5)09:12
azonenbergwpwrak: did i not commit after annotating it?09:12
azonenbergand these are indicator LEDs, you dont need a lot of current09:12
azonenbergi run 470 on most of mine and it works well09:13
azonenbergre the divider, that's the recommended termination from the datasheet09:13
azonenbergUG380 page 5209:13
azonenberg2*Z0 from SCK to Vdd and Vss09:14
Jialekernel: but I can not build lm32-gcc still, can you?09:15
Jiait didn't fix the bug, I think.09:15
wpwrakpag 52 ? don't see it mentioned. if it's in a drawing, my page 52 has "Figure 2-21: Spartan-6 FPGA BPI Configuration Waveforms"09:16
azonenbergBoard Layout for Configuration Clock (CCLK)09:16
azonenbergwhich doc version do you have? i'm reading v2.309:16
wpwrakv2.4 :)09:17
lekernelJia: didn't try... I have only been using clang+llvm+binutils lately09:17
Jialekernel: cool09:18
wpwrak(CCLK termination) interesting.09:20
azonenbergwpwrak: yeah, i didnt do that on any of my past boards09:20
azonenbergthe fpga booted fine09:20
azonenbergbut i noticed significant overshoot on the scope09:20
lekernelwe have it on the M1 (I remember that little mess), but I think it would work without09:20
lekernelit's not mentioned in all documentation versions (iirc)09:21
azonenbergi also noticed that the flash chip, rated for ~80 MHz operation, could only be used by user designs up to around 4009:21
azonenbergi was using on-chip termination for all of the data from me to the flash09:21
azonenbergi think that MISO needs termination too09:21
azonenbergi think i'm going to put a pad on there and i can always put a 0-ohm if it turns out to be unnecessary09:22
azonenberglekernel: also, my LA has just proven its worth http://i.imgur.com/0AAhe.png09:23
azonenbergthat's the bug in my memory controller09:23
azonenbergread is issued after a write but occurs before09:23
azonenbergso you end up reading what was there before the write happened09:23
lekernelbeware, DRAMs also need a bus turnaround time and a write recovery time when switching from write to read ...09:25
azonenberglekernel: the controller handles that fine09:25
azonenbergi've tested09:25
azonenbergthis is a bug in the glue that goes from my SoC's internal bus to the MCB09:26
azonenbergi intend to explore replacing this module and the mcb with something else later09:26
azonenbergthe wrapper is intended to make that easy should i choose to do so09:26
azonenbergin any case the sun is coming up so i'm off to get some sleep09:27
wpwrakyou may want to change the paths in *.pro09:28
wpwrakbasically sed s|/nfs/home/azonenberg/Documents/local/Electronics/kicad-|../../|09:29
wpwrakthe unannotated components are the mounting holes09:31
azonenbergwpwrak: interesting, they're P3-6 in my design09:35
azonenbergguess i never committed that version09:35
azonenbergwill do that after i do a final review of the design for things like power trace widths etc09:35
azonenbergand i had it set to absolute paths? Good catch09:36
wpwrakazonenberg: hmm, you could shrink the OHW logo and bring some I/Os out on a 100 mil header. easier for debugging (scope probes and such) than the small stuff09:48
wpwrakC19 is not very rework-friendly09:48
wpwrakazonenberg: is the bead really enough to make bead+220 uF silo behave like the 44 R+10 uF usb 2.0 allows ? (page 177, section 7.2.4.1)10:38
lekernelI'm reading up on DDR3 layout... http://www.fedevel.com/welldoneblog/2011/06/ddr3-memory-chip-mirroring-pcb-layout/10:46
lekernelsounds we can easily combine 2x 16-bit chips to make it look (almost) like a 32-bit chip and still it won't require write leveling10:47
lekernel(of course, this now requires BGA soldering on both sides of the PCB)10:48
lekernelso, with 4 of those combinations (which sounds feasible) and a artix-7, we have 140Gbps peak bandwidth, if it can take the SSO10:49
wpwrakSSO ?10:50
lekernelsimultaneously switching outputs10:50
wpwrakah ! one of those "new" parameters10:50
lekernelit causes ground bounce and power drops10:50
lekernelno, it's not new10:51
lekernelit's just that with so many I/Os that have to use the fastest slew rates (which causes the worst problems), we have to be careful10:51
wpwrak(new) yeah. it's just the sort of things i never saw before looking at the FPGA data sheets. of course, the underlying physics have been around for a bit :)10:57
ThihiSome billions of years ;p10:58
wpwrakyeah. the part still left to dispute is in the range of split-seconds rather than years :)10:59
ThihiA split second sounds so fast. We could talk about trillions of planck time units to get a nice big number.11:04
wpwrakindeed :)11:05
GitHub56[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/a49dcb328ab6c1f419e3fd04499f720146ac343b14:13
GitHub56[migen/master] actorlib/structuring/Cast: rawbits parameter - Sebastien Bourdeauducq14:13
GitHub21[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/iLsCVg14:13
GitHub21[milkymist-ng/master] framebuffer: chop memory words - Sebastien Bourdeauducq14:13
GitHub29[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/g8onuQ15:11
GitHub29[milkymist-ng/master] framebuffer: VTG and FIFO skeleton - Sebastien Bourdeauducq15:11
hellekinhello radical techies :)15:47
Action: larsc throws a cobblestone at hellekin 15:50
hellekinaie15:51
azonenbergwpwrak: i will definitely be adding some more headers17:51
azonenbergre the cap, good point17:51
wpwrakkewl17:51
azonenbergi'm used to running off wallwarts17:51
azonenbergand putting a ton of capacitance on17:51
azonenbergi probably dont need nearly that much before the reg if its running off a nice stable usb supply17:51
wpwrakmost hosts are fairly forgiving, but 220 uF may be pushing it17:52
azonenbergYeah17:52
azonenbergDebating whether to go with a 10uf ceramic or a 47uf tant17:52
azonenbergsince its after the bead17:52
wpwrakand they you can get fun effects like device power dancing around, with all the interesting things this may do to the FPGA's configuration process17:53
wpwrakagain voice of experience here - in openmoko, we once had a board with an FTDI that also had tons of caps. we spent a good amount of time figuring out why the FTDI would seem to lose its flash (or eeprom, don't remember) content every once in a while ...17:54
azonenberglol wow17:55
azonenbergyeah, i have a massive amount of capacitance on my SBC board17:55
azonenbergBut it's also a LX16/25 plus DDR memory so it needs it17:55
azonenbergand its running on a wallwart17:55
azonenbergGood suggestions, guys... i should get this done more often17:57
azonenbergGoing to fix up a bunch of stuff and add some debug points (scope ground clip etc)17:59
azonenbergthen commit an updated version in a few hours... if nobody sees any problems in that version i'll send it out for first-round fab17:59
lekernelazonenberg: if you like a challenge, I'll have the M3 board to get done ;)18:03
azonenbergi don't think i'm quite that good at layout yet lol18:03
azonenbergi wouldnt mind looking over it and offering suggestions18:03
azonenbergwhich fpga are you using on it?18:04
lekernelartix-718:04
lekernelazonenberg: btw I'm looking for potassium tantalate niobate (aka KTaNbO3 or KTN) crystals - any clues?18:06
azonenberglekernel: ooh, artix18:06
azonenbergdo you have a source for them yet or is this planning for the future?18:06
mumptaimhmm, for a laser scanner?18:07
lekernelplanning18:07
lekernelyes, for a laser scanner18:07
azonenbergAlso have you considered Zynq and, if you decided against it, what was your reasoning?18:07
lekernelI'm too cool for ARM18:08
azonenbergseems like the a9 would outperform LM32 by a huge margin18:08
mumptaiand is it still covered by the webpack style tools?18:08
azonenbergmumptai: yes18:08
azonenbergSo it's no less free than a proprietary FPGA with open RTL18:08
azonenberga proprietary CPU with open code18:08
lekernelthe RTL of that ARM is still closed18:09
azonenbergCorrect18:09
azonenbergbut so is the rtl for the boot loader on an FPGA that reads from SPI etc18:09
lekernelalso, I don't like the messy interfaces that usually come with proprietary IP18:09
azonenbergI do agree with that18:09
azonenbergI wasn't recommending it, just curious as to your reasoning18:09
lekernelproprietary RTL, highly dependent on one vendor, shitty interfaces18:09
lekernelthat rules it out for me18:09
azonenbergI see18:14
azonenbergre the crystals, no clue18:14
azonenbergi have a source for TaxClx18:14
azonenbergin ethanol solution18:14
azonenbergwhich upon spin coating and heating forms Ta2O5 for optical coatings, high-K, hardmasking, etc18:14
azonenbergthats the only tantalum compound i know where to get18:15
azonenbergwpwrak: ok, so now the bottom right area by the jtag header has a 2x4 header of GPIO21:05
azonenbergcap is 47uF21:05
azonenbergi'll be adding a scope ground clip and some probe pads shortly21:05
wpwrakyou stil need to fix the absolute paths in *.pro21:06
azonenbergOk21:06
azonenbergwpwrak: http://i.imgur.com/ZgxF4.png21:27
azonenbergadded a 2x4 header for GPIO (eight signals, no power/ground) plus a ground clip for a scope and a bunch of labeled probe pads on the power rails and clock21:28
azonenbergstill room for more probe pads in the upper right and between the fpga and jtag area21:28
azonenbergi just want to avoid breaking the ground plane under the GPIO traces at right center since those are LVDS capable and i want the option of decently high speed21:28
wpwrakyou really ought to include power on the header21:35
azonenbergSix signals / 3V3 / gnd?21:35
azonenbergi cant fit more than 8 pins there21:35
wpwrakput it in the upper right corner ?21:35
wpwrakthe bottom is way too crowded anyway21:35
azonenbergI'm puttnig stuff there too21:36
azonenbergi just dont want pins to go to waste21:36
wpwrakand the resistor facing the FPGA is nasty21:36
azonenbergwhich one?21:36
azonenbergthe one above the led bank? thats actually a cap21:37
mumptaiare the LDOs sufficient?21:37
azonenbergi run the same LDOs on my LX16 board21:37
azonenbergi wouldnt go any bigger but they're fine for a LX921:37
azonenbergHeader at bottom right is now 6 GPIO + 3V3 + gnd21:38
azonenbergmumptai: oh, and the LX16 board has DDR memory on it21:39
azonenbergwithout the RAM active it only pulls about 200 mA (800ish with the RAM going)21:39
azonenbergat max power they get up to 75C or so, a bit warm but well below the 125 upper limit21:39
wpwrakah yes, the cap. a bit messy to solder that way21:39
azonenbergI'll move it to the underside21:40
azonenbergthere are vias right there anywy21:40
mumptaik ;)21:40
wpwrakthat solves the problem :)21:40
wpwrakwhat will go in the upper right corner ?21:40
wpwrakand you still need to fix the absolute paths ;-)21:41
azonenbergyes, i know21:41
azonenberghttp://imgur.com/a/RjpwX#021:43
azonenbergfront and back21:43
azonenbergOne thing i have yet to add is a little white silkscreen region on the back21:45
azonenbergfor Sharpie-ing a serial number onto21:45
azonenbergi like to s/n all of my boards that i make mutiple units of so i can keep track of slight changes21:46
azonenbergfor example on one of my boards i put a lower density fpga on number 1 and 2/3 got the regular one21:46
mumptaimhmm, do your really want to connect the mounting-holes to the gnd-plane?21:46
azonenbergDepends on if you're connecting to a grounded enclosure or not21:47
azonenberg(for EMI reasons)21:47
azonenbergif you are not, you can always use a plastic washer21:47
azonenbergbut i figure it'd be nice to have the option of grounding it21:47
azonenbergif you disagree and can provide a good reason i'll certainly think about it21:48
mumptaiyou EMI performance might geht actually wore if you connect it to the case21:48
mumptai-h21:48
azonenberghmm, well my other board i made is not grounded on the holes21:48
mumptais/wore/worse/21:48
azonenbergi guess i can isolate them21:48
mumptaiif you connect gnd to the case, the connection is likely to become "critical" for emi, which most people don't like21:50
azonenberghmm ok21:50
mumptailocal shielding is typically prefered21:50
azonenbergi just know i've seen RF stuff with copper-painted cases21:50
azonenbergwhere the board has a via fence all around the edge that's screwed down21:50
mumptaisometimes 1M in parallel to 10pF are used21:51
azonenbergOk, fixed21:51
azonenbergalso added a silkscreen area on the back for writing in the s/n21:53
mumptaig'night21:55
azonenbergwolfspraul: how's it looking now?21:56
lekernelwhoa, $1100 per 5x5mm crystal at americanelements23:28
lekernelnice academic research prices, as always23:29
azonenberglekernel: lol is that expensive or cheap?23:30
wpwrakand then it drops by accident from your crowded table ... :)23:30
azonenbergalso, http://siliconexposed.blogspot.com/2012/06/isim-bugs-and-introducing-red-tin.html23:30
azonenbergalpha testers wanted23:31
lekernelsell two of them, and you have reimbursed your crystal furnace23:33
lekernelhttp://www.mtixtl.com/Multi-PsitionTubeFurnace1100C110V-GSL-1100X-110V.aspx23:33
azonenberglekernel: lol the furnace i was going to get was a 4 inch cube, only $120023:33
wpwrak"derating the simulator" nice. when you buy from xilinx, you can remember that some of your money goes to engineers that work specifically on making the products you're forced to use suck.23:34
azonenbergwpwrak: yeah lol23:34
azonenbergBut its not like altera or lattice or actel is any better23:35
azonenbergand boycotting programmable logic entirely isnt a viable option23:35
wpwrakso the others also put code into their "free" tools that cripples them ?23:40
azonenbergI believe so23:40
azonenbergI dont know specifically about simulation model line counts23:40
azonenbergi know the free ones have device capacity limitations23:40
azonenbergand people wonder why folks like wolfspraul are making their own tools? :P23:43
wolfspraullet's see how far I get23:43
azonenbergwolfspraul: http://imgur.com/a/RjpwX#023:44
wolfspraulI make a point of trying to not speak badly about other peoples work, I'm sure the Xilinx guys do good work on the ISE, and done23:44
azonenbergupdated version of the board23:44
wolfsprauland they seem to be on a major mission with Vivado23:44
wolfspraulbut working on tools is a great way for me to learn about the fpga, that's for sure :-)23:45
azonenbergi added a bunch of silkscreen text to label stuff, and added a 2x4 header at bottom right23:45
wolfspraulnice23:45
azonenbergplus a scope ground clip and probe pads on all power rails plus the clock23:45
azonenbergthere's not much i can fit in the top right23:46
azonenbergbecause the right side bank is mostly used23:46
wolfspraulI find the broken hardware symbol hilarious :-)23:46
azonenbergthe top bank is completely empty but i cant use it for anything since the power supply is in the way23:46
wolfspraulask 10 people what they think this is, and they will say it's maybe a logo for a hardware repair shop or so?23:46
wolfspraul:-)23:46
azonenberglol23:46
wolfspraulseriously23:46
azonenbergwell i felt like i had to put *something* there23:46
wolfspraulyou can try23:47
wolfspraulI actually like that logo because it is so funny23:47
azonenberglol23:47
azonenbergAnyway, last call for suggestions23:47
azonenbergi'm sending gerbers out to batch fab in an hour or two23:47
wolfspraulnone from me23:47
wolfspraulI probably need to make 50 or 100 or so of them :-)23:48
wolfspraulI'm sure when I start uploading my own designs into the chip I will damage chips, 100% sure23:48
wpwrakazonenberg: btw, this is for your vi: :%s#/nfs/home/azonenberg/Documents/local/Electronics/kicad-#../../#23:48
Action: azonenberg doesnt vi23:48
wpwrakah, that's why you were unable to fix the paths ;-)23:49
wolfspraulwhich editor do you use?23:49
Fallenouvery nice blog post azonenberg :)23:49
wolfspraulFallenou: hey good evening :-)23:49
Action: Fallenou tweeted it23:49
wolfspraulI see the various progress on the mmu, nice :-)23:49
wolfspraulin between talks with the boss, he he23:49
Fallenouhi !23:49
wolfsprauldid that go well for you?23:49
Fallenouactually the boss didn't show up23:50
wolfspraulthere you go23:50
Fallenouthe CTO replaced him for the talk :p23:50
Fallenoummu is making progress, still a few bugs to fix, and a few features to add23:51
Fallenoubut it's starting to look good :)23:51
wolfspraulI try to learn from your 'focused coding' culture23:51
wolfspraulso that I can squeeze out some progress when waiting for the bus, or some other smaller amounts of time here and there23:51
wolfspraulworks quite well23:51
wpwrakFallenou: did you think about the multiple ITLB misses in the pipeline issue ?23:51
Fallenouwolfspraul: good that it works for you too :) actually I did this because I had no time else than in the subway23:52
wolfspraulI try to catch up with you, but it's a good exercise23:52
Fallenouwpwrak: not yet, it's still stalled in my pipeline ;)23:52
FallenouI just spent 2 (or more) hours trying to "fix a bug" ... which was that I was running non-PIC code23:53
Fallenouwith ITLB enabled23:53
Fallenouafter having copied the code :)23:53
Fallenouso the first "calli" ... boom23:53
Fallenouwhen I understood how stupid it was I just facepalm23:54
wpwrakhah ! :-)23:54
wpwrakthat's what you get for copying code around ;-)23:54
Fallenou;)23:54
FallenouI am writting a small piece of code to "relocate" the code23:54
Fallenourewritting the calli/bi instructions as I copy them23:54
wpwrakargh :)23:55
FallenouI basically replaced the UART_CSR_RX_RX = '@'; by puts('@'); in the f() function23:55
Fallenouso now the code is much complex23:55
Fallenouand contains calli23:55
FallenouRX_TX***23:55
Fallenouwolfspraul: what is the short term goal of fpgatools ?23:56
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