| azonenberg | wolfspraul: that minimalistic LX9 board we talked about is in progress at http://code.google.com/p/azonenberg-devboards/source/list | 00:12 |
|---|---|---|
| wolfspraul | nice | 00:18 |
| azonenberg | so far i've just published my existing libraries (needed to do that anyway and this was a good excuse) as well as creating a skeleton schematic with a usb UART and some linear reg | 00:20 |
| azonenberg | i should have the sch done in an hour or so | 00:20 |
| wolfspraul | maybe we can mix and match a little with the milkymist kicad stuff, don't know | 00:23 |
| wolfspraul | at least on the library or style level, we see | 00:23 |
| azonenberg | ok | 00:30 |
| azonenberg | I'm releasing my board under BSD license btw | 00:31 |
| azonenberg | with a comment added in the LICENSE file to make it clear that "binary form" includes physical PCBs, gerbers, masks, or anything other than native CAD formats | 00:31 |
| wolfspraul | sure | 00:32 |
| wolfspraul | if you would ask 10 different people what that meant you'd get 10 different answers :-) | 00:33 |
| wolfspraul | and a few more from the same people the next day... | 00:34 |
| azonenberg | Lol | 00:34 |
| azonenberg | IANAL but i think this is pretty unambiguous http://pastebin.com/Zt59CErn | 00:34 |
| azonenberg | "The two categories combined are intended to encompass all possible uses of these designs." leaves little room for misunderstanding, i think | 00:36 |
| wpwrak | i wonder if there's a practical difference between 3-clause BSD and public domain ... | 01:14 |
| azonenberg | wpwrak: there is, they have to acknowledge your work | 02:22 |
| azonenberg | and then there's the "use at your own risk" clause which never hurts | 02:23 |
| azonenberg | But other than the acknowledgement requirement, not really | 02:23 |
| wpwrak | yeah, but i wonder if the acknowledgement has ever been actively enforced | 02:26 |
| wpwrak | and simply claiming somebody else's work probably conflicts with more general rights anyway. so that license may give you very little in practical terms. | 02:28 |
| azonenberg | wpwrak: yeah | 02:28 |
| azonenberg | But it's widely used and imposes virtually no restrictions that would result in someone choosing not to use it | 02:29 |
| azonenberg | Hence why i like it | 02:29 |
| azonenberg | wolfspraul: schematic done, starting layout | 02:30 |
| wolfspraul | :-) | 02:33 |
| wolfspraul | I'm typing faster | 02:33 |
| azonenberg | i included a few optional components (FT232, GPIO header, flash) that can be left off if you want a simpler/cheaper design | 02:33 |
| azonenberg | the area cost is near zero | 02:33 |
| azonenberg | device is bus powered (mini USB) | 02:33 |
| azonenberg | i'm going to add a ground clip for a scope plus a bunch of probe pads once i do rough-draft layout | 02:34 |
| wpwrak | azonenberg: i think the idea is to have a two board design: one board with just the FPGA (which wolfgang expects to destroy with his experiments) and another board with the more permanent components (power and such) | 02:35 |
| azonenberg | wpwrak: well i want to be able to use the board too | 02:36 |
| azonenberg | so i figure i'll just put on all the stuff | 02:36 |
| azonenberg | then document which parts can be left off | 02:36 |
| wpwrak | hehe :) | 02:36 |
| azonenberg | and i cnat imagine any failure mode that would destroy the rest of the board | 02:36 |
| azonenberg | reworking the chip is a matter of hot air and 5 minutes | 02:36 |
| wpwrak | if all is on the same board, you'd have to rework the fpga to swap it | 02:37 |
| azonenberg | wpwrak: the component count is minimal though | 02:37 |
| azonenberg | its just decoupling caps | 02:37 |
| azonenberg | which have to be on the fpga board itself | 02:37 |
| wpwrak | if it's two boards, you just toss the dead one and put in the new one | 02:37 |
| wpwrak | no regulators ? | 02:37 |
| azonenberg | the support stuff is literally three vregs and a jtag port | 02:37 |
| azonenberg | plus peripherals you can leave off (clock crystal, some LEDs, reset button, SPI flash) | 02:38 |
| azonenberg | and you'd have to solder the new fpga to a new board anyway | 02:42 |
| azonenberg | Taking an old one off with hot air is the work of 15 seconds | 02:42 |
| azonenberg | wolfspraul: it looks like it'll be around 4 in^2 btw | 02:57 |
| azonenberg | Trying to shrink but not sure how much i can do | 02:57 |
| azonenberg | the fpga itself is like a square inch by itself and i need room around it for routing lol | 02:57 |
| lekernel | grmbl http://www.xilinx.com/support/answers/31905.htm | 09:56 |
| lekernel | I was wondering how many DDR3 chips you can hook up to a artix-7 before hitting some limits... | 09:57 |
| lekernel | xilinx motto: "when it gets complex, obscurity helps". early FPGAs had detailed timing models in the datasheets... and now "just use our timing analyzer software" | 10:08 |
| GitHub102 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/dce00a02d17f239d211b3a4f0b002190197dd5e4 | 12:25 |
| GitHub102 | [migen/master] doc: performance tools - Sebastien Bourdeauducq | 12:25 |
| wpwrak | lekernel: high time for free and open synthesis. put an end to obscurity :) | 12:29 |
| GitHub39 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/95a0a313ba20683b3e2f721038dd0d597f128cd1 | 13:27 |
| GitHub39 | [migen/master] doc: ASMI topology - Sebastien Bourdeauducq | 13:27 |
| GitHub69 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/ed144199fee893d46d2bbc1d82ed34f7fc23b0e9 | 14:04 |
| GitHub69 | [migen/master] doc: interrupt controllers - Sebastien Bourdeauducq | 14:04 |
| azonenberg | wolfspraul: http://i.imgur.com/8pUkp.png | 22:35 |
| wolfspraul | with the broken hardware symbol :-) | 22:37 |
| wolfspraul | is the work finished? I mean the files in github? or you plan more? | 22:38 |
| azonenberg | wolfspraul: it's on google code | 22:39 |
| wolfspraul | if finished I will take a closer look. thanks a lot! I guess you will make some for verification, maybe I do the same here, need to go over the design first. | 22:39 |
| wolfspraul | this is very helpful | 22:39 |
| azonenberg | i've committed that version | 22:39 |
| wolfspraul | yes but do you think you are done for now? | 22:39 |
| azonenberg | the tinyurl goes straight to the SVN url for checking out the board files | 22:39 |
| azonenberg | and i am going to make one more verification pass | 22:39 |
| wolfspraul | ok | 22:39 |
| azonenberg | then send a run of 3 out to batch fab | 22:39 |
| azonenberg | lead time for fab+assembly+test will be around a month | 22:40 |
| wolfspraul | let me know when you think it's at a stable state, I guess that's soon or now | 22:40 |
| wolfspraul | bbiab | 22:40 |
| azonenberg | I'd appreciate a peer review before sending it out to fab | 22:40 |
| azonenberg | on the version in the repo | 22:40 |
| wolfspraul | excellent stuff, thanks a lot! | 22:40 |
| wolfspraul | yes | 22:40 |
| azonenberg | Just as a quick overview of what's on there - 3.3, 2.5, 1.2V regulators | 22:40 |
| azonenberg | mini USB port for power plus optional FT232RQ usb-uart | 22:41 |
| wolfspraul | have to run out, back in 20 | 22:41 |
| azonenberg | Ok | 22:41 |
| azonenberg | It also has eight LEDs, a reset switch (which needs a "RESET" label still), a 5x7mm CMOS oscillator, a W25Q80BV flash chip or similar, a 20-pin FFC connector for GPIO (same pinout as all of my other boards), the usual 2x7mm JTAG header | 22:42 |
| azonenberg | as well as 10-pin FFC, which is my experimental nonstandard low-profile JTAG solution (much smaller than the normal Molex connector) | 22:43 |
| azonenberg | i left the standard one on there too both as a backup and for easy interoperability | 22:43 |
| azonenberg | Grounded 4-40 mounting holes in each corner, inset 2mm from the edges of the PCB | 22:44 |
| azonenberg | i'm going to draw up a formal BOM including digikey part numbers for all components | 22:45 |
| kristianpaul | nice looking board azonenberg !! | 22:53 |
| azonenberg | kristianpaul: ty | 22:54 |
| azonenberg | it's intended as a fairly minimalistic spartan6 platform | 22:54 |
| azonenberg | drawing up a BOM workup now to find the per-unit cost | 22:54 |
| azonenberg | most of the components on there can be left off to cut costs if you dont need them | 22:55 |
| kristianpaul | you already made it or just planning right now? or just ordering parts? | 22:55 |
| azonenberg | Just finished the layout like 15 mins ago | 22:55 |
| kristianpaul | :-) | 22:55 |
| azonenberg | And i have all the parts except the FPGA in my inventory already | 22:55 |
| azonenberg | while i do have spartan6 in inventory now they're all FT256 package | 22:55 |
| azonenberg | so i'm gonna have to order some tqfp ones | 22:55 |
| Action: kristianpaul runs to take the bus | 22:57 | |
| wolfspraul | can the chip operate with less voltages, say only 1.2V? | 23:09 |
| wolfspraul | the ios will be 1.2 too then, I guess. if it works at all? | 23:09 |
| wolfspraul | can it generate a clock without the oscillator? | 23:09 |
| azonenberg | wolfspraul: unless you want to use ring oscillators (unstable and uncontrolled frequency) you'll need the osc | 23:10 |
| azonenberg | you need 1.2 for the core and 2.5 or 3.3 for vccaux (configuration, PLLs, and a few other things) | 23:11 |
| azonenberg | plus vccio | 23:11 |
| azonenberg | the osc i specified is a 3.3v part | 23:11 |
| azonenberg | so you'd need all 3 | 23:11 |
| azonenberg | i suppose you could remove the 2.5V reg and solder a wire from the 2.5V rail to the 3.3 | 23:12 |
| azonenberg | the chip can run at 3.3 on vccaux | 23:12 |
| azonenberg | but for saving 50 cents idk if it's worth it | 23:12 |
| wolfspraul | how unstable is a clock generated inside the fpga? | 23:13 |
| wolfspraul | actually I think the fpga can run on the jtag clock as well | 23:13 |
| azonenberg | you might be able to route it off CCLK i suppose | 23:13 |
| azonenberg | In any case i'm documenting the optional parts | 23:14 |
| azonenberg | in the BOM | 23:14 |
| wolfspraul | what is cclk and where does it come from? | 23:14 |
| wolfspraul | I ran past it a few times but still haven't understood the whole clock regime :-) | 23:14 |
| azonenberg | sorry, cclk isnt it | 23:15 |
| azonenberg | tck | 23:15 |
| azonenberg | typo | 23:15 |
| azonenberg | cclk is the clock the fpga supplies to an external SPI flash chip during boot | 23:15 |
| wolfspraul | where does it come from? | 23:15 |
| azonenberg | there's an oscillator on the fpga but to my knowledge it's not exposed onto the routing fabric | 23:15 |
| wolfspraul | maybe you can just leave that running for regular operation? | 23:17 |
| wolfspraul | cclk = configuration clock | 23:17 |
| azonenberg | i dont think its possible to | 23:17 |
| azonenberg | i think the configuration state machine shuts it off | 23:17 |
| azonenberg | Let me rephrase that | 23:18 |
| azonenberg | i am not aware of a documented and vendor-supported means of doing that | 23:18 |
| wolfspraul | ok | 23:20 |
| azonenberg | The decoupling network is probably overkill unless you're doing high speed stuff but it's basically right off their reference designs | 23:21 |
| azonenberg | for the LX9 | 23:21 |
| azonenberg | so i'm going to let sleeping dogs lie | 23:21 |
| Hawk777 | wolfspraul: if you're talking about Spartan 6 series, see page 63 in the Configuration datasheet; the STARTUP_SPARTAN6 primitive *does* provide access to the nominally-50 MHz (±50%) configuration clock | 23:42 |
| Hawk777 | probably something similar for other families | 23:43 |
| azonenberg | Hawk777: ooh | 23:43 |
| azonenberg | very interesting | 23:43 |
| wolfspraul | nice, thanks! | 23:43 |
| azonenberg | So highly variable, probably on-chip RC, but it is exposed | 23:43 |
| Hawk777 | yep! | 23:43 |
| Hawk777 | (never used it for anything myself so YMMV, but have fun) | 23:43 |
| wolfspraul | but I think I could even use the jtag clock as well | 23:44 |
| azonenberg | Not sure if it stops when the TAP isn't being probed | 23:44 |
| azonenberg | if you just plug the cable into a circuit does it start clocking it? | 23:44 |
| azonenberg | or is it only during a scan operation | 23:44 |
| wolfspraul | good question, don't know | 23:44 |
| azonenberg | from what i know of the jtag state machine, it has to not clock during some parts of the process | 23:45 |
| azonenberg | In any case, quick draft bom at http://code.google.com/p/azonenberg-devboards/source/browse/trunk/boards/minimal-spartan6-tq144/bom.txt | 23:45 |
| azonenberg | i'm still looking up digikey part numbers for some of the stuff and have yet to pretty it up (tabs to spaces, etc) | 23:45 |
| --- Fri Jun 29 2012 | 00:00 | |
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