#milkymist IRC log for Thursday, 2012-06-28

azonenbergwolfspraul: that minimalistic LX9 board we talked about is in progress at http://code.google.com/p/azonenberg-devboards/source/list00:12
wolfspraulnice00:18
azonenbergso far i've just published my existing libraries (needed to do that anyway and this was a good excuse) as well as creating a skeleton schematic with a usb UART and some linear reg00:20
azonenbergi should have the sch done in an hour or so00:20
wolfspraulmaybe we can mix and match a little with the milkymist kicad stuff, don't know00:23
wolfspraulat least on the library or style level, we see00:23
azonenbergok00:30
azonenbergI'm releasing my board under BSD license btw00:31
azonenbergwith a comment added in the LICENSE file to make it clear that "binary form" includes physical PCBs, gerbers, masks, or anything other than native CAD formats00:31
wolfspraulsure00:32
wolfspraulif you would ask 10 different people what that meant you'd get 10 different answers :-)00:33
wolfsprauland a few more from the same people the next day...00:34
azonenbergLol00:34
azonenbergIANAL but i think this is pretty unambiguous http://pastebin.com/Zt59CErn00:34
azonenberg"The two categories combined are intended to encompass all possible uses of these designs." leaves little room for misunderstanding, i think00:36
wpwraki wonder if there's a practical difference between 3-clause BSD and public domain ...01:14
azonenbergwpwrak: there is, they have to acknowledge your work02:22
azonenbergand then there's the "use at your own risk" clause which never hurts02:23
azonenbergBut other than the acknowledgement requirement, not really02:23
wpwrakyeah, but i wonder if the acknowledgement has ever been actively enforced02:26
wpwrakand simply claiming somebody else's work probably conflicts with more general rights anyway. so that license may give you very little in practical terms.02:28
azonenbergwpwrak: yeah02:28
azonenbergBut it's widely used and imposes virtually no restrictions that would result in someone choosing not to use it02:29
azonenbergHence why i like it02:29
azonenbergwolfspraul: schematic done, starting layout02:30
wolfspraul:-)02:33
wolfspraulI'm typing faster02:33
azonenbergi included a few optional components (FT232, GPIO header, flash) that can be left off if you want a simpler/cheaper design02:33
azonenbergthe area cost is near zero02:33
azonenbergdevice is bus powered (mini USB)02:33
azonenbergi'm going to add a ground clip for a scope plus a bunch of probe pads once i do rough-draft layout02:34
wpwrakazonenberg: i think the idea is to have a two board design: one board with just the FPGA (which wolfgang expects to destroy with his experiments) and another board with the more permanent components (power and such)02:35
azonenbergwpwrak: well i want to be able to use the board too02:36
azonenbergso i figure i'll just put on all the stuff02:36
azonenbergthen document which parts can be left off02:36
wpwrakhehe :)02:36
azonenbergand i cnat imagine any failure mode that would destroy the rest of the board02:36
azonenbergreworking the chip is a matter of hot air and 5 minutes02:36
wpwrakif all is on the same board, you'd have to rework the fpga to swap it02:37
azonenbergwpwrak: the component count is minimal though02:37
azonenbergits just decoupling caps02:37
azonenbergwhich have to be on the fpga board itself02:37
wpwrakif it's two boards, you just toss the dead one and put in the new one02:37
wpwrakno regulators ?02:37
azonenbergthe support stuff is literally three vregs and a jtag port02:37
azonenbergplus peripherals you can leave off (clock crystal, some LEDs, reset button, SPI flash)02:38
azonenbergand you'd have to solder the new fpga to a new board anyway02:42
azonenbergTaking an old one off with hot air is the work of 15 seconds02:42
azonenbergwolfspraul: it looks like it'll be around 4 in^2 btw02:57
azonenbergTrying to shrink but not sure how much i can do02:57
azonenbergthe fpga itself is like a square inch by itself and i need room around it for routing lol02:57
lekernelgrmbl http://www.xilinx.com/support/answers/31905.htm09:56
lekernelI was wondering how many DDR3 chips you can hook up to a artix-7 before hitting some limits...09:57
lekernelxilinx motto: "when it gets complex, obscurity helps". early FPGAs had detailed timing models in the datasheets... and now "just use our timing analyzer software"10:08
GitHub102[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/dce00a02d17f239d211b3a4f0b002190197dd5e412:25
GitHub102[migen/master] doc: performance tools - Sebastien Bourdeauducq12:25
wpwraklekernel: high time for free and open synthesis. put an end to obscurity :)12:29
GitHub39[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/95a0a313ba20683b3e2f721038dd0d597f128cd113:27
GitHub39[migen/master] doc: ASMI topology - Sebastien Bourdeauducq13:27
GitHub69[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/ed144199fee893d46d2bbc1d82ed34f7fc23b0e914:04
GitHub69[migen/master] doc: interrupt controllers - Sebastien Bourdeauducq14:04
azonenbergwolfspraul: http://i.imgur.com/8pUkp.png22:35
wolfspraulwith the broken hardware symbol :-)22:37
wolfspraulis the work finished? I mean the files in github? or you plan more?22:38
azonenbergwolfspraul: it's on google code22:39
wolfspraulif finished I will take a closer look. thanks a lot! I guess you will make some for verification, maybe I do the same here, need to go over the design first.22:39
wolfspraulthis is very helpful22:39
azonenbergi've committed that version22:39
wolfspraulyes but do you think you are done for now?22:39
azonenbergthe tinyurl goes straight to the SVN url for checking out the board files22:39
azonenbergand i am going to make one more verification pass22:39
wolfspraulok22:39
azonenbergthen send a run of 3 out to batch fab22:39
azonenberglead time for fab+assembly+test will be around a month22:40
wolfspraullet me know when you think it's at a stable state, I guess that's soon or now22:40
wolfspraulbbiab22:40
azonenbergI'd appreciate a peer review before sending it out to fab22:40
azonenbergon the version in the repo22:40
wolfspraulexcellent stuff, thanks a lot!22:40
wolfspraulyes22:40
azonenbergJust as a quick overview of what's on there - 3.3, 2.5, 1.2V regulators22:40
azonenbergmini USB port for power plus optional FT232RQ usb-uart22:41
wolfspraulhave to run out, back in 2022:41
azonenbergOk22:41
azonenbergIt also has eight LEDs, a reset switch (which needs a "RESET" label still), a 5x7mm CMOS oscillator, a W25Q80BV flash chip or similar, a 20-pin FFC connector for GPIO (same pinout as all of my other boards), the usual 2x7mm JTAG header22:42
azonenbergas well as 10-pin FFC, which is my experimental nonstandard low-profile JTAG solution (much smaller than the normal Molex connector)22:43
azonenbergi left the standard one on there too both as a backup and for easy interoperability22:43
azonenbergGrounded 4-40 mounting holes in each corner, inset 2mm from the edges of the PCB22:44
azonenbergi'm going to draw up a formal BOM including digikey part numbers for all components22:45
kristianpaulnice looking board azonenberg !!22:53
azonenbergkristianpaul: ty22:54
azonenbergit's intended as a fairly minimalistic spartan6 platform22:54
azonenbergdrawing up a BOM workup now to find the per-unit cost22:54
azonenbergmost of the components on there can be left off to cut costs if you dont need them22:55
kristianpaulyou already made it or just planning right now? or just ordering parts?22:55
azonenbergJust finished the layout like 15 mins ago22:55
kristianpaul:-)22:55
azonenbergAnd i have all the parts except the FPGA in my inventory already22:55
azonenbergwhile i do have spartan6 in inventory now they're all FT256 package22:55
azonenbergso i'm gonna have to order some tqfp ones22:55
Action: kristianpaul runs to take the bus22:57
wolfspraulcan the chip operate with less voltages, say only 1.2V?23:09
wolfspraulthe ios will be 1.2 too then, I guess. if it works at all?23:09
wolfspraulcan it generate a clock without the oscillator?23:09
azonenbergwolfspraul: unless you want to use ring oscillators (unstable and uncontrolled frequency) you'll need the osc23:10
azonenbergyou need 1.2 for the core and 2.5 or 3.3 for vccaux (configuration, PLLs, and a few other things)23:11
azonenbergplus vccio23:11
azonenbergthe osc i specified is a 3.3v part23:11
azonenbergso you'd need all 323:11
azonenbergi suppose you could remove the 2.5V reg and solder a wire from the 2.5V rail to the 3.323:12
azonenbergthe chip can run at 3.3 on vccaux23:12
azonenbergbut for saving 50 cents idk if it's worth it23:12
wolfspraulhow unstable is a clock generated inside the fpga?23:13
wolfspraulactually I think the fpga can run on the jtag clock as well23:13
azonenbergyou might be able to route it off CCLK i suppose23:13
azonenbergIn any case i'm documenting the optional parts23:14
azonenbergin the BOM23:14
wolfspraulwhat is cclk and where does it come from?23:14
wolfspraulI ran past it a few times but still haven't understood the whole clock regime :-)23:14
azonenbergsorry, cclk isnt it23:15
azonenbergtck23:15
azonenbergtypo23:15
azonenbergcclk is the clock the fpga supplies to an external SPI flash chip during boot23:15
wolfspraulwhere does it come from?23:15
azonenbergthere's an oscillator on the fpga but to my knowledge it's not exposed onto the routing fabric23:15
wolfspraulmaybe you can just leave that running for regular operation?23:17
wolfspraulcclk = configuration clock23:17
azonenbergi dont think its possible to23:17
azonenbergi think the configuration state machine shuts it off23:17
azonenbergLet me rephrase that23:18
azonenbergi am not aware of a documented and vendor-supported means of doing that23:18
wolfspraulok23:20
azonenbergThe decoupling network is probably overkill unless you're doing high speed stuff but it's basically right off their reference designs23:21
azonenbergfor the LX923:21
azonenbergso i'm going to let sleeping dogs lie23:21
Hawk777wolfspraul: if you're talking about Spartan 6 series, see page 63 in the Configuration datasheet; the STARTUP_SPARTAN6 primitive *does* provide access to the nominally-50 MHz (±50%) configuration clock23:42
Hawk777probably something similar for other families23:43
azonenbergHawk777: ooh23:43
azonenbergvery interesting23:43
wolfspraulnice, thanks!23:43
azonenbergSo highly variable, probably on-chip RC, but it is exposed23:43
Hawk777yep!23:43
Hawk777(never used it for anything myself so YMMV, but have fun)23:43
wolfspraulbut I think I could even use the jtag clock as well23:44
azonenbergNot sure if it stops when the TAP isn't being probed23:44
azonenbergif you just plug the cable into a circuit does it start clocking it?23:44
azonenbergor is it only during a scan operation23:44
wolfspraulgood question, don't know23:44
azonenbergfrom what i know of the jtag state machine, it has to not clock during some parts of the process23:45
azonenbergIn any case, quick draft bom at http://code.google.com/p/azonenberg-devboards/source/browse/trunk/boards/minimal-spartan6-tq144/bom.txt23:45
azonenbergi'm still looking up digikey part numbers for some of the stuff and have yet to pretty it up (tabs to spaces, etc)23:45
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