#milkymist IRC log for Wednesday, 2012-06-27

GitHub141[board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/e688f6ca2351d623247af6f5644a2325ad509c8101:20
GitHub141[board-m1/master] added 'PowerTree' for pdf generation - Adam Wang01:20
cladamw(R60/R61) wpwrak, hi these two DNP resistors I'd like to remove them. R61(DNP) has been designed since rc1 and there's no issues on this as I know. R60(DNP) is from rc3 for eliminating reset/nor corruption issue. How do you think ?01:32
wpwraklemme see ...01:34
wpwrakR60 definitely yes. even if we wanted a pull-anything there, it would be pull-down.01:37
wpwrakR61, hmm ... do you remember the pull-up strength in the FPGA ?01:42
cladamwlike uA-class, letmme check ...01:44
cladamwno, from actual measured current to 3V3 through 100 ohm, they are for example TP37 (RP#, 16mA), TP36(reset pin out, 19mA), INIT_B_2 (24.7mA)01:55
wpwrakthat doesn't sound like pull-up :)01:56
cladamwyeah ... :-)01:57
wpwrakah, here we are .. DS162, page 5. 200-500 uA01:58
cladamwyes, that's Irpu, you found it. :-)02:01
wpwrakso about 10 kOhm. R61 is thus unnecessary, too.02:03
cladamwdo we need also check U9.STS pin ?02:04
wpwrakit's open-drain02:07
cladamwi guessed that R61 was being added a pull-up since its datasheet said it needs a pull-up there. :-)02:08
cladamwpage 1402:08
wpwrakwe have the pull-up in the fpga :)02:11
cladamwsee also page 15 for note 6, but i think fpga in a mode with pull-up ability, no ? so a flash chip is in "pulled up by an external pull up resistance H10k) when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset power-down mode."02:11
wpwrakand it's strong enough. even if we configure the nor to pulse mode, it has plenty of time to ramp up.02:12
cladamwso even if we know fpga inside has pull-up, ha ~ but i don't know 'when' it's being acted. :-)02:12
wpwrakthe pull-up in the fpga is enabled in the configuration we use02:13
cladamwso can i say once fpga has been reconfigured then flash chip jumps into 'no-pull up' need status ?02:13
cladamwwell ... i don't quite figure out that true answer why it is though. :-) but from results since rc1, we can remove it. :-)02:16
wpwrakwhen configured, the fpga provides the external (from the NOR's point of view) pull-up02:16
wpwrakand before it's configured, it doesn't care about status (see UG380, page 48)02:17
wpwrakso yes, should be safe to remove02:18
wpwrakin pulse mode, the signal would look like this: http://downloads.qi-hardware.com/people/werner/tmp/flash_sts.ps02:22
cladamwso this means that if we are not using fpga that possesses pull-up ability ans used a microprocessor. we still need to check carefully on the initial and/or default once power-up on mcu side.02:23
wpwrakbut our requirements may be more relaxed. i don't see flash_sts being used anywhere in the core. so we don't really know if it works.02:24
wpwrakyes, if you make radical changes to the circuit, there will be many things that need checking ;-))02:24
cladamwyou means you didn't find 'any' sts pins in fpga ? :-)02:25
wpwrakoh, i see it in boards/milkymist-one/synthesis/common.ucf and boards/milkymist-one/rtl/system.v02:25
wpwrakbut that's all02:25
cladamwaha ... at least this .v expresses that http://en.qi-hardware.com/wiki/File:M1rc2_powerOnOff_sequences_manuscript.jpg i recorded. :-)02:29
cladamwwpwrak, alright, thanks for chats on it. :)02:29
wpwrakmy pleasure :)02:32
cladamwwpwrak, about flash_sts.ps, how did you know to use R1 = 0.1 ohm and C1 for 12pF ? I see a Cin for DIE input capacitance at the pad max. is 10pF in DS162, so you added a rough 2pF for stray capacitance, correct ?02:41
wpwrakoh, i used maximum in and out capacitance of the NOR (5+7 pF)02:45
wpwrak10 pF is a bit more. so let's make it 15 pF. yeah, a bit uglier.02:46
wpwrakR1 (0.1 Ohm) is simply to give qucs some resistance. it doesn't like circuits that are too "ideal".02:47
wpwrakthe value of R1 is not critical. it pretty much works the same with R1 = 100 Ohm.02:47
cladamwoh ~ when doing a simulation, we'd better to take consideration on both side circuits, theoretically right ? so this simulation, C1 is more like in total: (Cinput + Coutput, 12 pF) for STS pin + (Cin, 10pF) for fpga + (stray cap., said 2~3pF), am I right ? )02:50
cladamw(R1) i see, tks. :)02:51
wpwrak(cap) on the NOR side, you only need Coutput = 5 pF. i used the NOR's Cin as an approximation for the FPGA, because i was too lazy to look up that one.02:53
cladamwoh ~ no problem, I was just tried to realize how those values being picked when learning simulations in Qucs. :-) so it's typically for NOR side simulation. :)02:59
GitHub175[board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/8e6ae7e6ef3bd6ceea8673b3afe67f4fba9114c504:08
GitHub175[board-m1/master] removed R60(DNP), R61(DNP); - Adam Wang04:08
GitHub21[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/a50df0a6ed741db0a838e5764b33be034606a17d22:46
GitHub21[migen/master] doc: link df simulation example - Sebastien Bourdeauducq22:46
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