| GitHub141 | [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/e688f6ca2351d623247af6f5644a2325ad509c81 | 01:20 |
|---|---|---|
| GitHub141 | [board-m1/master] added 'PowerTree' for pdf generation - Adam Wang | 01:20 |
| cladamw | (R60/R61) wpwrak, hi these two DNP resistors I'd like to remove them. R61(DNP) has been designed since rc1 and there's no issues on this as I know. R60(DNP) is from rc3 for eliminating reset/nor corruption issue. How do you think ? | 01:32 |
| wpwrak | lemme see ... | 01:34 |
| wpwrak | R60 definitely yes. even if we wanted a pull-anything there, it would be pull-down. | 01:37 |
| wpwrak | R61, hmm ... do you remember the pull-up strength in the FPGA ? | 01:42 |
| cladamw | like uA-class, letmme check ... | 01:44 |
| cladamw | no, from actual measured current to 3V3 through 100 ohm, they are for example TP37 (RP#, 16mA), TP36(reset pin out, 19mA), INIT_B_2 (24.7mA) | 01:55 |
| wpwrak | that doesn't sound like pull-up :) | 01:56 |
| cladamw | yeah ... :-) | 01:57 |
| wpwrak | ah, here we are .. DS162, page 5. 200-500 uA | 01:58 |
| cladamw | yes, that's Irpu, you found it. :-) | 02:01 |
| wpwrak | so about 10 kOhm. R61 is thus unnecessary, too. | 02:03 |
| cladamw | do we need also check U9.STS pin ? | 02:04 |
| wpwrak | it's open-drain | 02:07 |
| cladamw | i guessed that R61 was being added a pull-up since its datasheet said it needs a pull-up there. :-) | 02:08 |
| cladamw | page 14 | 02:08 |
| wpwrak | we have the pull-up in the fpga :) | 02:11 |
| cladamw | see also page 15 for note 6, but i think fpga in a mode with pull-up ability, no ? so a flash chip is in "pulled up by an external pull up resistance H10k) when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset power-down mode." | 02:11 |
| wpwrak | and it's strong enough. even if we configure the nor to pulse mode, it has plenty of time to ramp up. | 02:12 |
| cladamw | so even if we know fpga inside has pull-up, ha ~ but i don't know 'when' it's being acted. :-) | 02:12 |
| wpwrak | the pull-up in the fpga is enabled in the configuration we use | 02:13 |
| cladamw | so can i say once fpga has been reconfigured then flash chip jumps into 'no-pull up' need status ? | 02:13 |
| cladamw | well ... i don't quite figure out that true answer why it is though. :-) but from results since rc1, we can remove it. :-) | 02:16 |
| wpwrak | when configured, the fpga provides the external (from the NOR's point of view) pull-up | 02:16 |
| wpwrak | and before it's configured, it doesn't care about status (see UG380, page 48) | 02:17 |
| wpwrak | so yes, should be safe to remove | 02:18 |
| wpwrak | in pulse mode, the signal would look like this: http://downloads.qi-hardware.com/people/werner/tmp/flash_sts.ps | 02:22 |
| cladamw | so this means that if we are not using fpga that possesses pull-up ability ans used a microprocessor. we still need to check carefully on the initial and/or default once power-up on mcu side. | 02:23 |
| cladamw | s/ans/and | 02:24 |
| wpwrak | but our requirements may be more relaxed. i don't see flash_sts being used anywhere in the core. so we don't really know if it works. | 02:24 |
| wpwrak | yes, if you make radical changes to the circuit, there will be many things that need checking ;-)) | 02:24 |
| cladamw | you means you didn't find 'any' sts pins in fpga ? :-) | 02:25 |
| wpwrak | oh, i see it in boards/milkymist-one/synthesis/common.ucf and boards/milkymist-one/rtl/system.v | 02:25 |
| wpwrak | but that's all | 02:25 |
| cladamw | aha ... at least this .v expresses that http://en.qi-hardware.com/wiki/File:M1rc2_powerOnOff_sequences_manuscript.jpg i recorded. :-) | 02:29 |
| cladamw | wpwrak, alright, thanks for chats on it. :) | 02:29 |
| wpwrak | my pleasure :) | 02:32 |
| cladamw | wpwrak, about flash_sts.ps, how did you know to use R1 = 0.1 ohm and C1 for 12pF ? I see a Cin for DIE input capacitance at the pad max. is 10pF in DS162, so you added a rough 2pF for stray capacitance, correct ? | 02:41 |
| wpwrak | oh, i used maximum in and out capacitance of the NOR (5+7 pF) | 02:45 |
| wpwrak | 10 pF is a bit more. so let's make it 15 pF. yeah, a bit uglier. | 02:46 |
| wpwrak | R1 (0.1 Ohm) is simply to give qucs some resistance. it doesn't like circuits that are too "ideal". | 02:47 |
| wpwrak | the value of R1 is not critical. it pretty much works the same with R1 = 100 Ohm. | 02:47 |
| cladamw | oh ~ when doing a simulation, we'd better to take consideration on both side circuits, theoretically right ? so this simulation, C1 is more like in total: (Cinput + Coutput, 12 pF) for STS pin + (Cin, 10pF) for fpga + (stray cap., said 2~3pF), am I right ? ) | 02:50 |
| cladamw | (R1) i see, tks. :) | 02:51 |
| wpwrak | (cap) on the NOR side, you only need Coutput = 5 pF. i used the NOR's Cin as an approximation for the FPGA, because i was too lazy to look up that one. | 02:53 |
| wpwrak | http://downloads.qi-hardware.com/people/werner/tmp/flash_sts2.ps | 02:54 |
| cladamw | oh ~ no problem, I was just tried to realize how those values being picked when learning simulations in Qucs. :-) so it's typically for NOR side simulation. :) | 02:59 |
| GitHub175 | [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/8e6ae7e6ef3bd6ceea8673b3afe67f4fba9114c5 | 04:08 |
| GitHub175 | [board-m1/master] removed R60(DNP), R61(DNP); - Adam Wang | 04:08 |
| GitHub21 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/a50df0a6ed741db0a838e5764b33be034606a17d | 22:46 |
| GitHub21 | [migen/master] doc: link df simulation example - Sebastien Bourdeauducq | 22:46 |
| --- Thu Jun 28 2012 | 00:00 | |
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