#milkymist IRC log for Tuesday, 2012-06-26

Fallenouhi there17:41
Fallenouit has been some time I haven't seen any usb commit :) any upcoming surprise ? :)17:41
Fallenouis there some work in progress about usb soft stack ?17:42
Fallenouor is it stalled ?17:42
wpwrakFallenou: there seems to be little point in adding features to softusb. once your mmu works, we can make linux run nicely and give it a proper USB host (which will have to be different from the current softusb)20:29
Fallenouyes indeed20:41
FallenouI didn't want to stop softusb improvements though :'20:41
Action: Fallenou starts to feel the heavy responsabilities on his shoulders20:42
wpwrakwhy not ? everybody is very happy to have a good excuse for not sinking more time into it ;-))20:42
sh4rm4it would be nice tho if softusb worked well20:49
Fallenoulet's hope I will achieve a stable state and a stable Linux then :)20:49
Fallenouanyway linux or not we need the navre/softusb low lever usb signaling to work well , right ?20:49
Fallenouis the low level stuff perfectly ok now ?20:49
Fallenoulevel*20:49
wpwrakFallenou: i'd do it that way, yes. another approach may be to make a "hard" host controller, which would probably be faster. but also more work.20:52
wpwrakFallenou: low-level seems to be much better now20:53
wpwrakthe main source of trouble are now fancy report formats and hubs. both are the sort of problem we should let linux worry about :)20:53
wpwraksoftusb will probably need a DMA interface for decent performance20:55
sh4rm4hmm lekernel's new OS plan doesnt seem to involve linux20:55
wpwraki guess he'll come around the second linux is stable (and fast) ;-)20:56
Fallenouahah I hope someone will ever use lm32-mmu and linux =)21:07
Fallenouwpwrak: I have a code configuration where the itlbtest (running the f function with itlb enable) works , even with relocation21:09
FallenouI need to map (in itlb) the whole (used) nand21:10
Fallenouthis works well if mmu_map (which registers in an array in the bios the mappings in order to put them back in *TLB upon any *TLB miss) pushes the mapping in the TLB right away21:11
Fallenouif I do "lazy" mapping21:11
Fallenouthen it crashes (soc hang)21:11
FallenouI suspect a NULL page being asked on wishbone bus by either inst_fetch or data_fetch21:11
Fallenoubut I could not reproduce it (for now) in ISim to understand why a NULL page gets asked21:12
FallenouI even implemented the same kind of "if NULL is asked I do a $display() and hang the SoC" in my simulation SoC21:12
Fallenouin order to detect such problems21:12
Fallenourunning approx. the same itlbtest() in ISim does not trigger any NULL page21:13
Fallenoubut maybe the devil is in the details :)21:13
Fallenouanyway it's quite nice how well it works in ISim, even with lazy mapping (which means tons of TLB misses and exception to handle the mappings), I guess with a few "FPGA only" bugs corrected it should work as well on the FPGA :)21:15
mwalleFallenou: btw whats the reason not to use verilator/iverilog?21:16
Fallenoulekernel: is it on purpose that you don't activate cache associativity "2" ? synthesis fails ?21:17
Fallenoumwalle: iverilog faild to simulate lm32, I started with iverilog before trying ISim21:17
Fallenoumwalle: verilator ... I don't remember if I tried, is it free ? easy to grab ?21:18
Fallenouworks on Linux ?21:18
mwalleFallenou: acutally i meant cver21:19
mwallegplcver21:19
Fallenoudescription seems nice :21:20
Fallenou:)21:20
FallenouI didn't try, maybe I should21:20
Fallenouthanks for the link21:20
mwalleFallenou: iirc lekernel simulated the lm32 with it21:20
Fallenougreat :)21:22
mwallemh maybe not21:22
mwallei'm confused, sorry ;)21:22
FallenouI must say, proprietary or not, ISim has done quite a nice job for me for now21:22
wpwrakFallenou: does your definition of NULL match the SoC's ? iirc, the condition is anything < 128*1024.21:29
FallenouI did the same thing21:29
Fallenouif ((i_adr_o[31:18] == 14'd0 && wishbone_ibus_ack) || (d_adr_o[31:18] == 14'd0 && wishbone_dbus_ack))21:30
Fallenouthen display() and set high the wishbone_err_o21:30
wpwrakhmm. then it's tricky :)21:31
Fallenouhttp://pastebin.com/14jiFBtJ21:32
FallenouI had this one nice21:32
FallenouBios was still alive after the test =)21:32
wpwrakso it sometimes works and sometimes not ?21:33
Fallenouit depends on the events21:33
Fallenouon if I do lazy tlb mappings or not21:33
Fallenouif I do lazy mappings on DTLB or ITLB or both21:33
wpwraki wonder if the exception gets properly synchronized with the pipeline. it that exception basically handled like an interrupt ?21:36
Fallenouthe exception is (I hope) handled like other exceptions21:36
Fallenouhttps://github.com/fallen/milkymist-mmu/blob/mmu/cores/lm32/rtl/lm32_cpu.v#L177421:37
Fallenouand line 180021:37
Fallenouand then line 185021:37
FallenouDTLB has its own exception vector (and EID of course)21:38
FallenouITLB as well but I did not push any ITLB stuff on milkymist-mmu repository yet cause it still has bugs on fpga :)21:38
Fallenouhttps://github.com/fallen/milkymist-mmu-simulation/blob/master/lm32_cpu.v#L1821 https://github.com/fallen/milkymist-mmu-simulation/blob/master/lm32_cpu.v#L1871 if you want to see with ITLB as well21:40
Fallenouwpwrak: to answer fully your question, in lm32 an interrupt is triggering an exception, interrupt stuff is using a given exception ID21:40
Fallenouor exception vector21:41
Fallenouso yes in fine ITLB/DTLB are triggering an exception, just like an interrupt would21:42
wpwraki wonder if the pipeline is properly synchronized. how many stages does lm32 have ? something like fetch, reg read, execute, reg write ?21:42
Fallenou6 stages21:43
Fallenouaddress, fetch, decode, execute, memory, write back21:43
Fallenouthe execute stage triggers exception (via exception_x)21:43
Fallenoubut the cpu really branches only if exception_x gets propagated to exception_m (the next stage)21:44
Fallenouand it only does if the correct combinaison of stage stalling is OK (and branch conditions etc etc etc)21:44
Fallenouit only does so*21:45
wpwrakso that would be for breakpoint, divide by zero, etc.21:45
wpwrakin the case of the ITLB, the exception would be raised in the address or fetch stage21:46
wpwrakso the "we're in an exception" information would have to be passed along (delayed) by some more stages21:46
Fallenouhum well why delaying it ?21:48
Fallenouwe are fetching from an unmapped address21:48
Fallenouwe need to do something immediately, no ?21:48
Fallenoubut yes that could be wrong in case of a branch (and wrong branch prediction)21:49
Fallenouthat would just mean we would trigger a "tlb miss" for nothing but it should not kill anything21:50
Fallenouboth "results" of a test-and-branch should be mapped I guess21:50
wpwrakwhat about the preceding instructions that are still in the pipeline ?21:52
Fallenouafter exception handled I jumb back to where PC_x was21:53
Fallenouso I get the same pipeline "configuration"21:53
Fallenouand then execution resumes21:53
wpwrakhmm. assume we have instructions FOO, BAR, BLAH, and TROUBLE. in this order. if you raise the exception in fetch, then TROUBLE would be in fetch, BLAH would be in decode, BAR in execute, FOO in memory. each of which would still have work to do. are you sure they leave the pipeline cleanly ?21:55
FallenouFOO is just "fetch" which does not change internal cpu state21:57
FallenouBAR is decode, it's the same (reg read)21:57
FallenouBLAH is executed anyway21:57
Fallenouwhen I return from exception it goes like this BLAH is fetched, then BAR BLAH, then FOO BAR BLAH and here we are again21:58
Fallenousame configuration21:58
Fallenoumaybe I'm not seing something21:59
Fallenouin theory an interrupt could happen anytime, it would raise an exception too22:00
Fallenouand it would not mess the pipeline :o22:00
Fallenouis this proving something ?22:00
wpwrakthe order is reversed. you have FOO, BAR, BLAH, then TROUBLE. by the time TROUBLE hits fetch, FOO is already almost done, BAR a little less, etc.22:01
Fallenouoh OK you were stating the other way22:02
Fallenousorry I missread you :)22:02
wpwraki wonder about interrupts :) in theory, you could treat them like an exception of the instruction that's executing (which is where i suppose breakpoint, divide by zero, and such happen)22:02
Fallenouyes that's it22:02
Fallenouexception of the instruction in X stage22:02
Fallenouso when it returns it jumps back to PC_X + 1 or something like that22:02
Fallenouor PC_X22:03
Fallenouit jumps back to PC_X sorry22:04
Fallenouit does EA = PC_X and then PC_F = exception_vector (and kills other instructions from the pipeline)22:04
Fallenouand then when returning from exception, it does PC_F = EA (and kills other instructions from the pipeline)22:05
wpwrakso ... what happens with the half-finished instructions ?22:06
wpwrakyou just repeat them ? if yes, could they have had a side-effect in their first life ?22:06
Fallenouinstructions in stage "MEM" and "WB" do whatever they want in their stage (like the one in X stage)22:06
Fallenoubut the pipeline does not go forward anymore22:07
wpwrake.g., change status register bits, initiate a memory write22:07
Fallenousee page 29 of the datasheet22:08
FallenouExceptions occur in the execute pipeline stage. If there is an instruction in the memory pipeline stage, that instruction is first allowed to finish. All instructions from the Execute stage back are then killed and do not cause any user- transparent state changes. For example, no flags are set.22:08
wpwrakokay. and what if the exception is in fetch ?22:09
Fallenouwell the exception is due to something happening in "fetch", but the exception occures as if it was caused by "execute"22:09
Fallenouit should do the same thing22:09
wpwrakmaybe adding some NOPs could change how successful your code is :)22:10
wpwrak(exception in fetch) so you carry the "this instruction is exceptional" information along ?22:10
Fallenouno no22:10
Fallenousorry I am explaining this badly22:10
Fallenoulet say from left to right : address | fetch | decode | exec | mem | write back22:11
Fallenoulet say instructions are A B C D E F22:11
Fallenouif A triggers an ITLB exception (in fetch stage)22:11
FallenouI instantly raise "exception_x"22:12
Fallenouso it's as if instruction D has caused an exception in stage execute22:12
Fallenouand it's as if an interrupt happened from some GPIO22:12
wpwrakyou mean if your code is F; E; D; C; B; A; ? :)22:12
Fallenouyes22:13
wpwrakif A is in fetch (raising an exception), then B is in decode, C in exec, right ?22:15
Fallenoudo you think there might be a problem with this way of raising "instantly" exception_x, even if the real cause of the exception is in fetch ?22:15
Fallenouah yes sorry22:15
FallenouI was counting "address"22:16
Fallenouyes it's not D but C22:16
Fallenouwhich is in exec22:16
wpwraki wonder what happens to the instructions in decode and execute22:16
Action: Fallenou is tired a bit22:16
wpwraki.e., B and C22:16
Fallenouwell C finishes it's execution, but does not change any flag22:16
Fallenouand B never reaches the execution stage22:17
wpwrakah, but you reset the PC to where C has been22:17
Fallenouyes22:17
wpwrakso this PC can be quite different from the ITLB fault address22:17
Fallenouupon returning I do "bi address_of_C"22:17
Fallenouwhich is "bi EA" (or eret)22:18
Fallenouyes22:18
wpwrakokay. that sounds correct then.22:18
Fallenouit can be different, it depends on if there is a branch somewhere22:18
Fallenouknowing that AFAIK lm32 is doing "I take branch anyway as a prediction"22:19
Fallenoubranches are "taken"22:19
wpwrakthe should always be at least a little different. since it's the address of A, not of C22:19
Fallenouyes sure22:19
larsci think backward branches are predicted as taken, forward branches as not taken22:19
Fallenouah yes maybe22:20
FallenouI forgot exactly what was the algorithm :)22:20
Fallenouwpwrak: itlb stuff seems pretty OK in ISim, so unless I am kind of lucky with my pipelines (which could be right) the present implementation sounds ok22:21
wpwrakcould this happen ? A gets an ITLB fault. you handle it. then the exception handling "rewinds" to C. then you get an ITLB fault for C.22:23
Fallenouit could if A and C are aliases for the TLB22:24
Fallenouand the A handling expulses the C mapping from TLB22:24
Fallenouoh god22:24
wpwrakyup :) (or if B had an issue too and evicted C)22:24
FallenouI guess you discovered a "itlb storm" issue ?22:25
wpwrak(not sure if you can have this sort of triple ITLB misses, though. depends on how branches are done.)22:25
wpwrak;-)))22:25
FallenouI will think about that situation :)22:25
Fallenouit's becoming late here22:25
Fallenouand tomorrow I have to be at the office early because I meet with the boss :p22:25
wpwraklet's hope it's for a promotion :)22:26
Fallenouhehe nop22:26
wpwrakat least a pay rise ?22:26
Fallenoufor an official talk and presentation of the numerous department22:26
Fallenousince I'm "new"22:26
Fallenou(6-8 months in the company)22:26
wpwraksome kind of "new" ;-)22:27
Fallenouit takes the whole day22:29
Fallenouproductivity drop22:29
wpwrakwow. a big company then.22:32
Fallenouyes pretty big :)22:35
Fallenoufor a french tech company22:35
Fallenou~500 engineers22:35
wpwraknot too bad. they must have many toys then :)22:39
Fallenousure :)22:39
Fallenougn8!23:07
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