kristianpaul | wee | 01:32 |
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kristianpaul | package for urjtag seems to work on F17 :D | 01:32 |
kristianpaul | at least for BIOS flashing.. lets try soemthing bigger and wipeout flash too | 01:35 |
wolfspraul | my god | 01:52 |
wolfspraul | what should we do? | 01:52 |
wolfspraul | distribute some valium among community members to avoid over-excitement? | 01:52 |
Action: kristianpaul hide | 01:55 | |
kristianpaul | s | 01:56 |
kristianpaul | no need for valium, i just took a nap :) | 01:57 |
kristianpaul | about urjtag, well, one the less thing i have to compile by hand also get more value /to my self/ to my FEL installation :) | 01:59 |
GitHub44 | [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/913232ef43982aff8c9529ad116fbfe91ef17268 | 02:42 |
GitHub44 | [board-m1/master] Power_Tree.sch: added currents - Adam Wang | 02:42 |
lekernel | azonenberg: have you read this? http://download.micron.com/pdf/technotes/DDR/tn4614.pdf | 09:04 |
lekernel | there are a couple of pages on vref | 09:05 |
GitHub78 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/920aa5dc60c0cccd706a51f480a70c845a58b4bf | 09:37 |
GitHub78 | [migen/master] actorlib: merge composer into ala + derive ComposableSource from ActorNode - Sebastien Bourdeauducq | 09:37 |
GitHub126 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/fa5a9915c3eaf5235411e3b0ea5f912f1c731ef7 | 14:10 |
GitHub126 | [migen/master] doc: actor network - Sebastien Bourdeauducq | 14:10 |
azonenberg | lekernel: i've read a bunch of appnotes, let me see that one | 15:12 |
azonenberg | Well they very strongly recommend 6-layer (3S3P or 4S2P) stackups in most cases lol | 15:13 |
azonenberg | so i'm already violating most of their guidelines by using 2 layers :p | 15:13 |
azonenberg | sorry, 2 signal layers | 15:13 |
azonenberg | 2S2P on 4 layers | 15:13 |
azonenberg | oh, and lack of controlled impedance | 15:16 |
azonenberg | But i dont think that at 240 MT/s (120 MHz) that wil.l matter quite as much as 400 MT/s 200 MHz | 15:16 |
wpwrak | a true luddite would use a single-sided FR2 board and mount the chips on DIP adapters | 15:17 |
azonenberg | wpwrak: not for DDR memory lol | 15:17 |
azonenberg | I was getting ~160mV peak to peak ripple on my SSTL Vref | 15:17 |
wpwrak | did i mention running everything at 5 V ? ;-) | 15:18 |
azonenberg | put 10nF across the output of the regulator (right by the reg, the RAM is about 1/2" away and the FPGA 1-2" away) and ripple went down but i still am getting a lot of bit corruption | 15:18 |
azonenberg | once i'm fully awake i'm gonna put another 10nF across the other side of the Vref bus near the FPGA | 15:18 |
Fallenou | put 10nF everywhere :p | 15:18 |
azonenberg | i dont want to put the board under the knife until i'm awake | 15:18 |
azonenberg | lol | 15:18 |
azonenberg | i also dont know for sure if Vref is the only problem | 15:18 |
wpwrak | yeah. the more caps, the merrier | 15:18 |
azonenberg | i know i was getting crosstalk on Vref from DQ1 | 15:19 |
Fallenou | and make sure to put the capacitances very near the DDR chip pins | 15:19 |
azonenberg | they're routed worryingly close | 15:19 |
azonenberg | Fallenou: http://i.imgur.com/tEL3p.png | 15:19 |
azonenberg | this is top and bottom copper only with ground fills hidden | 15:19 |
azonenberg | LP2995 reg outputs two independent 1.25V lines for Vtt and Vref (the SOIC8 at top left near the big tant caps) | 15:19 |
azonenberg | Vref runs on bottom layer (green) down the left side of the board | 15:19 |
azonenberg | under the DDR chip, then in to the FPGA at the bottom left | 15:20 |
wpwrak | kicad .. nice. did you route manually or with freeroute ? | 15:20 |
azonenberg | this area here http://i.imgur.com/9yJYe.png is where i think noise is getting in | 15:20 |
azonenberg | all manual | 15:20 |
azonenberg | http://i.imgur.com/vhcBU.png shows that there's ground between the Vref trace and all other signal routing | 15:20 |
azonenberg | this is the full bottom layer including ground fills | 15:21 |
azonenberg | Vref is the long snaky trace on the left | 15:21 |
azonenberg | http://i.imgur.com/q7Jls.jpg is the assembled board (not that that will tell you much) | 15:21 |
azonenberg | its an 8 bit data bus and i'm testing with 0x00FF00FF since thats worst case crosstalk from DQ* to other signals and worst-case SSO | 15:21 |
wpwrak | is that the only ground layer ? | 15:21 |
azonenberg | No | 15:22 |
wpwrak | good :) | 15:22 |
azonenberg | Stackup is signal and ground fill on top | 15:22 |
azonenberg | then a power plane broken in a few spots (mostly under the DDR chip and between it and the FPGA) for extra signal routing | 15:22 |
azonenberg | then solid ground broken only by via antipads | 15:22 |
azonenberg | then the green layer, signal with ground fill | 15:22 |
wpwrak | perfect | 15:23 |
azonenberg | all main components are on top copper except for the INA226 current shunt monitors (under the power supply area at top left) | 15:23 |
azonenberg | most small bypass caps are on the bottom but all of the big tantalum/ceramic tank caps are on top | 15:23 |
azonenberg | when i write 0x00FF00FF to the bus with no capacitance on Vref, it read back as 00FB00FF (I don't know whether the write or read was corrupted, that's still being investigated) | 15:26 |
azonenberg | My oscilloscope is 1Gsa/s with 100 MHz bandwidth so DDR at 120 MHz/240 MT/s is a little fast | 15:27 |
azonenberg | http://imgur.com/a/HC7Cf#4 shows Vtt Vref DQ0 left to right | 15:27 |
azonenberg | and bus idle and active top to bottom | 15:27 |
azonenberg | when i put the capacitance on, Vref ripple dropped by a lot but the test data read as 00F800FF (even worse!) | 15:28 |
azonenberg | the wrong values are consistent across all tests i've run so far | 15:28 |
azonenberg | i need to get time on a faster scope... | 15:28 |
wpwrak | does any significant time pass between write and read ? | 15:53 |
kristianpaul | about crosstalk, is not LVDS good enought those days to implement serial ram memories for < 100Mhz range? | 16:36 |
wpwrak | if you can afford the pin count ... | 17:09 |
wpwrak | ah, you said serial | 17:10 |
lekernel | well, if you see behaviour changes when adding decoupling... you definitely have power integrity issues | 22:46 |
--- Tue Jun 26 2012 | 00:00 |
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