#milkymist IRC log for Monday, 2012-06-25

kristianpaulpackage for urjtag seems to work on F17 :D01:32
kristianpaulat least for BIOS flashing.. lets try soemthing bigger and wipeout flash too01:35
wolfspraulmy god01:52
wolfspraulwhat should we do?01:52
wolfsprauldistribute some valium among community members to avoid over-excitement?01:52
Action: kristianpaul hide01:55
kristianpaulno need for valium, i just took a nap :)01:57
kristianpaulabout urjtag, well, one the less thing i have to compile by hand also get more value /to my self/ to my FEL installation :)01:59
GitHub44[board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/913232ef43982aff8c9529ad116fbfe91ef1726802:42
GitHub44[board-m1/master] Power_Tree.sch: added currents - Adam Wang02:42
lekernelazonenberg: have you read this? http://download.micron.com/pdf/technotes/DDR/tn4614.pdf09:04
lekernelthere are a couple of pages on vref09:05
GitHub78[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/920aa5dc60c0cccd706a51f480a70c845a58b4bf09:37
GitHub78[migen/master] actorlib: merge composer into ala + derive ComposableSource from ActorNode - Sebastien Bourdeauducq09:37
GitHub126[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/fa5a9915c3eaf5235411e3b0ea5f912f1c731ef714:10
GitHub126[migen/master] doc: actor network - Sebastien Bourdeauducq14:10
azonenberglekernel: i've read a bunch of appnotes, let me see that one15:12
azonenbergWell they very strongly recommend 6-layer (3S3P or 4S2P) stackups in most cases lol15:13
azonenbergso i'm already violating most of their guidelines by using 2 layers :p15:13
azonenbergsorry, 2 signal layers15:13
azonenberg2S2P on 4 layers15:13
azonenbergoh, and lack of controlled impedance15:16
azonenbergBut i dont think that at 240 MT/s (120 MHz) that wil.l matter quite as much as 400 MT/s 200 MHz15:16
wpwraka true luddite would use a single-sided FR2 board and mount the chips on DIP adapters15:17
azonenbergwpwrak: not for DDR memory lol15:17
azonenbergI was getting ~160mV peak to peak ripple on my SSTL Vref15:17
wpwrakdid i mention running everything at 5 V ? ;-)15:18
azonenbergput 10nF across the output of the regulator (right by the reg, the RAM is about 1/2" away and the FPGA 1-2" away) and ripple went down but i still am getting a lot of bit corruption15:18
azonenbergonce i'm fully awake i'm gonna put another 10nF across the other side of the Vref bus near the FPGA15:18
Fallenouput 10nF everywhere :p15:18
azonenbergi dont want to put the board under the knife until i'm awake15:18
azonenbergi also dont know for sure if Vref is the only problem15:18
wpwrakyeah. the more caps, the merrier15:18
azonenbergi know i was getting crosstalk on Vref from DQ115:19
Fallenouand make sure to put the capacitances very near the DDR chip pins15:19
azonenbergthey're routed worryingly close15:19
azonenbergFallenou: http://i.imgur.com/tEL3p.png15:19
azonenbergthis is top and bottom copper only with ground fills hidden15:19
azonenbergLP2995 reg outputs two independent 1.25V lines for Vtt and Vref (the SOIC8 at top left near the big tant caps)15:19
azonenbergVref runs on bottom layer (green) down the left side of the board15:19
azonenbergunder the DDR chip, then in to the FPGA at the bottom left15:20
wpwrakkicad .. nice. did you route manually or with freeroute ?15:20
azonenbergthis area here http://i.imgur.com/9yJYe.png is where i think noise is getting in15:20
azonenbergall manual15:20
azonenberghttp://i.imgur.com/vhcBU.png shows that there's ground between the Vref trace and all other signal routing15:20
azonenbergthis is the full bottom layer including ground fills15:21
azonenbergVref is the long snaky trace on the left15:21
azonenberghttp://i.imgur.com/q7Jls.jpg is the assembled board (not that that will tell you much)15:21
azonenbergits an 8 bit data bus and i'm testing with 0x00FF00FF since thats worst case crosstalk from DQ* to other signals and worst-case SSO15:21
wpwrakis that the only ground layer ?15:21
wpwrakgood :)15:22
azonenbergStackup is signal and ground fill on top15:22
azonenbergthen a power plane broken in a few spots (mostly under the DDR chip and between it and the FPGA) for extra signal routing15:22
azonenbergthen solid ground broken only by via antipads15:22
azonenbergthen the green layer, signal with ground fill15:22
azonenbergall main components are on top copper except for the INA226 current shunt monitors (under the power supply area at top left)15:23
azonenbergmost small bypass caps are on the bottom but all of the big tantalum/ceramic tank caps are on top15:23
azonenbergwhen i write 0x00FF00FF to the bus with no capacitance on Vref, it read back as 00FB00FF (I don't know whether the write or read was corrupted, that's still being investigated)15:26
azonenbergMy oscilloscope is 1Gsa/s with 100 MHz bandwidth so DDR at 120 MHz/240 MT/s is a little fast15:27
azonenberghttp://imgur.com/a/HC7Cf#4 shows Vtt Vref DQ0 left to right15:27
azonenbergand bus idle and active top to bottom15:27
azonenbergwhen i put the capacitance on, Vref ripple dropped by a lot but the test data read as 00F800FF (even worse!)15:28
azonenbergthe wrong values are consistent across all tests i've run so far15:28
azonenbergi need to get time on a faster scope...15:28
wpwrakdoes any significant time pass between write and read ?15:53
kristianpaulabout crosstalk, is not LVDS good enought those days to implement serial ram memories for < 100Mhz range?16:36
wpwrakif you can afford the pin count ...17:09
wpwrakah, you said serial17:10
lekernelwell, if you see behaviour changes when adding decoupling... you definitely have power integrity issues22:46
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