#milkymist IRC log for Monday, 2012-06-11

lekernelFallenou: hmm, we should move the mmu stuff to -ng I think.07:39
Fallenouyou mean I should rewrite it in python using migen framework ?08:00
Fallenouor that I should commit mmu stuff in milkymist-ng/verilog/lm32 ?08:22
lekernelno no, the mmu stays in verilog08:38
lekernelI mean, just integrate it in the -ng code base (which shouldn't be difficult)08:38
lekernelI'll create a mmu branch and do it for you... will be the occasion for some testing/review08:45
FallenouOk fine :)08:55
FallenouI need to add a few `ifdef CFG_MMU_ENABLED at a few places08:55
Fallenou11:01 < Fallenou> Ok fine :)08:55
Fallenouand refactor a little bit the code08:55
Fallenoulekernel: the recent ITLB commits have made previous dtlb tests obsolete. They don't willingly activate ITLB, but at the return of the first "DTLB miss" it enables both ITLB and DTLB. And then a storm of endless ITLB misses :)19:31
FallenouI will need to fix "detest" and "dtlbtest"19:32
Fallenouthey don't work anymore19:32
Fallenouif you only look at https://github.com/fallen/milkymist-mmu/commits/mmu ; then it's OK, I didn't commit any ITLB stuff in there yet :)19:33
FallenouITLB stuff is only on the "simulation project" for now19:33
Fallenouso dtlb tests should still be OK in milkymist-mmu repo19:34
Action: Fallenou is putting `ifdef CFG_MMU_ENABLED everywhere20:02
Fallenoulekernel: what's best to initialize regs, reg NAME = VALUE; or doing a if (rst_i) NAME <= VALUE; in the driving always @(posedge clk_i) ?20:28
Fallenouthe second one uses less logic ?20:29
Fallenouor can go to ASIC ? or something like that ?20:29
kristianpaulno name = value;20:35
kristianpaulyou need do that on reset20:35
kristianpaulname = value; <- i wonder hoe get sinthesized on asic :-)20:35
FallenouOK that's what I thought20:35
Fallenouthanks20:35
kristianpaulperhpas in migen this reset logi is done automatically by reg = value;  ^_^20:37
kristianpaullogic*20:38
larscyea, another annoyance. I want a language which has native support for clockdomains and reset values and instantiates whatever is best for my target architecture20:40
larsc(and where it is an error to pass a signal from one clock domain to antother without proper synchronization)20:43
kristianpaulhe :)20:44
kristianpaulA SoC description language... ?20:51
larsca proper highlevel hdl language20:52
larscuhm20:52
larscs/ language//20:52
kristianpaulyup20:52
kristianpaulperhaps is not a language it self, just lack of more depth verification from the tools20:57
kristianpaulwhere are the lints tools..20:58
Fallenoumaybe just do a few tools of static/dynamic analysis :)20:59
Fallenoucoverity / cococinel etc20:59
larsci want a proper language. development in vhdl/verilog is like writing for example sw in asm instead of C20:59
Fallenoucoccinelle*20:59
Fallenoumaybe migen can reach the level of feature/maturity you are searching for eventually :)21:00
kristianpaulah xst have a -cross_clock_analysis21:01
larscmaybe21:01
kristianpaulbut no worth get too much used to it perhaps21:01
kristianpaulFallenou: indeed21:01
larscunfortunately migen ist a AST generator and not a language21:03
kristianpaulcan you make a equivalent problem like CDC but in C?21:04
kristianpauland how the language specificaion aid/helps to solve it?21:05
kristianpaulcause i see more like a lack of integration of tools in the development workflow21:05
kristianpaulthere is a flow indeed, but you still need to get details of every step to know when something got wrong21:06
kristianpaullarsc: or fpga still a very limited resource device21:09
kristianpauljust like when you use asm because cant affort allocate memory for C21:09
larsci'm quite convinced that you waste more resources by writing suboptimal hdl code21:10
larscjust as most modern c compilers will write way more effective asm code than a human does21:12
Fallenougn8 !21:14
lekernellanguage (eg CAL) will come... but for some stuff you need HDL21:31
lekernelmigen already takes care of reset values btw22:11
lekernelFallenou: and yes, use if(rst_i)22:12
lekernelreg xx = value has a (different) meaning on FPGA (register is initialized during bitstream load) but cannot be implemented on asic at all22:12
--- Tue Jun 12 201200:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!