#milkymist IRC log for Monday, 2012-06-04

lekernelwpwrak: yeah, yeah, continue being sarcastic. meanwhile, linux/x11 don't work while rtems/mtk do (also using cooperative multitasking for the UI by the way)09:26
lekerneldone in a more messy way than with lua coroutines even09:27
lekernelI agree that it won't work in the general case, it's enough here.09:29
lekernels/it's/but it's09:29
lekernelalso 100% of the linux UIs are shitty, so it has to be NIH. so why the bickering? :)09:29
FallenouNIH = ?09:32
Fallenounot invented here ?09:32
lekernelmwalle: not much difference, simply using the migen CSR bank generator09:33
lekernelFallenou: yes09:33
Fallenouabout MMU, I thought we did not want to check for page permissions ?09:48
Fallenoudo we add 3 permission bits ? (read write execute) ?09:48
lekernelexecute definitely not - the way to make something executable or not is by mapping it or not in the itlb09:49
lekernelread/write yes09:50
lekernelwpwrak: why do you want to track the _page_'s dirty status?10:02
lekernelI assume you meant the associated cache lines, which makes sense for a write back cache...10:02
GitHub131[milkymist] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/milkymist/commit/95a82041432f573319c9fa7fc57b0ac15243948f10:18
GitHub131[milkymist/master] softusb: interrrupt support for navre - Michael Walle10:18
Fallenouit seems the cache is behaving correctly right now, it's part of the test "detest"11:30
FallenouI map a->a, I write 42 to a, I read back from a, I write 43 to b, I map a->b, I read back from a, and it reads 43 , not 4211:31
Fallenouand without any cache flush11:34
lekernelwhen writing, you are reading the TLB, then sending the write directly and immediately on the bus, right?11:35
Fallenouyes I did not change the way the cache works11:39
Fallenouit's still write through11:39
Fallenouit's written both on the bus and in the cache at the same time11:40
Fallenoutlb does its lookup when the instruction is still in the X stage11:40
Fallenouso that when the instruction reaches the M stage, the tlb lookup is already done and ready11:41
Fallenoujust like the cache in fact11:41
lekernelhow do you inhibit the write into the cache on a TLB miss?11:43
lekernel(you'll see... itlb will be easier ;) read only, no permission bits, ...)11:45
Fallenou13:50 < lekernel> how do you inhibit the write into the cache on a TLB miss? < I can't see where it's done in the code so I guess it's not done and it's a bug :) I will test that ! thanks for pointing that out11:46
FallenouI would just do something like assign write_port_enable = ((refill_ready == `TRUE) || !stall_m) && ~dtlb_miss;11:47
Fallenou(add the && ~tlb_miss)11:47
Fallenouthere https://github.com/fallen/milkymist-mmu/blob/mmu/cores/lm32/rtl/lm32_dcache.v#L56911:47
lekernelthe problem is the write is already done when the TLB data becomes available11:58
lekernelmaybe the solution would be to revert the write on a TLB miss11:58
lekernelor invalidate the whole cache line11:58
wpwraklekernel: (dirty) it's for swapping, rw-mapping files, and so on. the memory manager needs to know when a page has changed so that it only has to write things that have actually changed.11:59
lekernelif you want to implement #1, it is possible to configure block-RAMs so that they output the previous data on a write11:59
lekernelyou just have to describe it in the verilog, and the synthesizer will (usually) do the right thing11:59
wpwraklekernel: you can assume all pages are dirty, but i'd expect this to be pretty inefficient11:59
Fallenouyes I've seen that in Xst doc11:59
lekerneljust do whatever is easier... since you have to run slow software on a TLB miss, the performance gain of #1 over #2 is negligible12:01
wpwraklekernel: (nih) i'm a bit surprised you suddenly see a need to go in a new direction with the underlying OS. linux infrastructure is coming along nicely, so why spend now weeks on reinventing the ROM BASIC ?12:01
lekernelmaybe you could even modify the cache control system to let the software invalidate individual lines12:01
FallenouI think it should be pretty easy to allow invalidating cache lines12:02
Fallenouit's already possible to invalidate just one TLB line12:02
lekernelwould save you the pain of implementing the little stall cpu/multiplex cache control/invalidate line sequencer in hardware12:02
wpwrak(NIH) and RTEMS seems give little enough trouble at the moment that there doesn't seem to be a pressing need to abandon it in a hurry12:02
lekernelwpwrak: one of the points is also to evaluate LLVM, and building RTEMS with clang is messy12:03
lekernelnot because of LLVM but because of autocrap12:03
FallenouI guess a CC=clang isn't enough ? :)12:03
lekernelwith my last clang patch, in theory it should be enough... except you also need -ccc-host-triple lm32-elf in the cflags12:04
wpwraki have my hopes set on autocrap behaving a little better on linux. at least the OS environment will be known. but yes, autocrap will be more visible on linux.12:04
lekerneland autocrap is all about prefixing tool names (e.g. lm32-elf-xxxx), not passing the arch in the cflags12:05
lekernelso much for something meant to make software portable ...12:05
lekernelwpwrak: calling it a "rom basic" is a bit like calling a ferrari a renault 4L12:09
lekernelbesides, I'm not reinventing much - it's a lot of libs and copy and paste - except stuff like the graphics/rendering toolkit which is non-existent in linux anyway12:10
stekernlekernel: do you need the -ccc-host-triple if you make a symlink called lm32-elf-clang?12:12
lekernelmaybe not... but I like the -ccc-host-triple. having one compiler per architecture while >80% of the code is shared is stupid.12:14
lekernelwpwrak: is the javascript in your browser a rom basic as well? :)12:16
stekernwell, it still the same compiler with all the targets compiled in. i.e. lm32-elf-clang == clang -ccc-host-triple lm3212:16
stekernyou can still run clang -ccc-host-triple mips if you like12:17
lekernelsure. but why keep the gcc legacy, except for supporting inane tools like autocrap?12:17
lekernelbesides I'm pretty sure there will be other problems12:17
stekernoh, yes, probably12:18
lekernelFallenou: I kinda like the software cache line invalidation. otherwise you need to mux cache access, stall the CPU, etc.12:30
lekernelmore LUTs, more delay (ie less MHz), more complexity, more probablity of nasty bugs12:31
lekernelif you implement the per-line invalidation, maybe you can even remove the current mechanism that invalidates the whole cache (it's just a counter + sequencer)12:33
lekernelyou could do that counter in software. not sure how slow it will be compared to the hardware counter, though.12:33
wpwrak(rom basic) i mean as a simple language that's "hardwired" into the platform12:38
lekerneltake it as an additional means of doing modifications12:39
wpwrakand the silly javascript in my brower is that i rarely have to worry about it, let alone write a libc for it ;-)12:39
lekernelthe rest of the software is still open source, and you are free to modify it - if you feel like installing a toolchain, recompiling, etc.12:40
lekernelalso, lua allows you not to worry about things like memory management, annoying C string manipulations, etc.12:41
Fallenouif it's working correctly I think it's best to keep the hardware implementation for invalidating the whole cache13:18
Fallenouit's really more efficient13:18
wpwraki'm not against lua. one can probably learn it in a day.13:19
Fallenoubut yes OK I will add a way to invalidate just one cache line, I will need to be smart to multiplex CSR though :) it's a scarce resource13:19
wpwraki just find it odd that you write your own operating system around it13:19
FallenouI'm already doing different things whether you rcsr or wcsr with the same CSR ID13:20
Fallenourcsr dtlbvaddr gives you the virtual address of latest page fault, wcsr dtlbvaddr writes to the dtlb_vaddress_reg register which is used to set up a mapping13:20
Fallenouor to invalidate a line13:20
Fallenouin the rcsr dtlbvaddr case I defined an alias "dtlbma" (dtlb miss address) to "dtlbvaddr" in binutils in order to keep source code readability13:21
lekernelFallenou: when you write to DCC, you give a register no?13:21
lekerneliirc the value is ignored atm13:22
Fallenouafaik yes the value is ignored13:22
lekernelyou can say that if bit 31 is set, then it only invalidates one line determined by the other bits in that reg13:22
Fallenoua simple write is enough to trigger invalidation13:22
Fallenouhum that breaks software compatibility but ok13:22
lekernelwho cares13:22
Fallenouok =)13:23
FallenouI'm already using that kind of trick for DTLBCTRL csr13:23
lekerneland iirc software uses r0 atm, so it wouldn't even break13:23
Fallenouif bit 31 is set it's targetting DTLB, if not it's targetting ITLB13:23
lekernelmaybe "DTLBCTRL" is a ill-chosen name then :)13:37
Fallenouit's TLBCTRL actually13:42
Fallenouto help spot problems with the MMU, in parallel of writting "hard written" test sequences, I will implement a few commands to directly play with the MMU from the bios prompt14:53
Fallenoulike "map", "invalidate"14:54
Fallenoumemory read and memory write are already implemented afaik14:54
Fallenouso that one can directly try a scenario by just entering a few commands14:54
Fallenouto check if it's supported or behaving correctly :)14:54
Fallenoulike write there, map this, read back there, invalidate this etc etc14:55
Fallenouit won't spot tricky timing problems, but will spot big implementation problems :)14:55
Fallenoucache coherency and such14:55
wpwraksounds reasonable14:56
Fallenouand quick to implement :14:57
Fallenouhelpful and quick14:57
wpwrakyou may want to do cached and uncached reads and maybe even writes, so that you can also set up or test unusual situations14:57
Fallenouwpwrak: I think I may not have understood all your emails about page dirty and such, I may ask you some questions about it later ^^14:58
wpwraksure :)14:58
wpwrakmy memory on those things is a bit dated. i looked into paging quite a bit when i implemented "zero-copy" for ATM, but that was about 16 years ago15:00
FallenouI was still drinking milk15:11
wpwraklinux was still in its infancy back then as well ;-)15:24
lekernelI remember running your LILO on my 486 :)15:28
Fallenouwpwrak: you are the original author of LILO ?15:45
wpwrakFallenou: yup :)15:59
Fallenouohoh I used it too :p but not on my 486 ^^16:02
GitHub186[milkymist-ng] sbourdeauducq pushed 3 new commits to master: http://git.io/y_bdnA17:46
GitHub186[milkymist-ng/master] software/base/limits.h: add some more - Sebastien Bourdeauducq17:46
GitHub186[milkymist-ng/master] base/stdlib.h: abs/labs - Sebastien Bourdeauducq17:46
GitHub186[milkymist-ng/master] software/libbase: qsort - Sebastien Bourdeauducq17:46
GitHub45[misp] sbourdeauducq pushed 2 new commits to master: http://git.io/_baF6w17:53
GitHub45[misp/master] liblua/Makefile: cleanup - Sebastien Bourdeauducq17:53
GitHub45[misp/master] Add Freetype - Sebastien Bourdeauducq17:53
kristianpaulhmm, do we have framwbuffer already?18:24
kristianpaulmissing a file to push in clang ?18:28
lekernelhmm I believe it should have been built from ./tools/clang/include/clang/Basic/DiagnosticSerializationKinds.td18:32
kristianpauli'll start over again just in case18:33
kristianpaulbut clang in build inside llvm right?18:42
lekernelyou should put the clang sources in a directory called "clang" in llvm/tools18:42
kristianpaulyup right there it is18:44
GitHub196[misp] sbourdeauducq pushed 1 new commit to master: http://git.io/fdp-cw18:57
GitHub196[misp/master] Define properly the Freetype config - Sebastien Bourdeauducq18:57
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