#milkymist IRC log for Monday, 2012-04-09

GitHub179[board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/1ffa9cd0e12be65b338895c08ea18516f748654a00:53
GitHub179[board-m1/master] added .gitignore file - Adam Wang00:53
wolfspra1lcladamw: good morning!00:54
cladamwgood morning :)00:55
wolfspra1leverything alright on your end? do you need any help?00:56
cladamwno need now. :-)00:57
wolfspra1lok good00:58
cladamw1. I'll create initial Hierarchical Sheet for M1, it means to include all schematic empty sheets firstly00:58
cladamw2. since the house sent me file already, so after hierarchical sheet, I'll back to review the placement then feedback to them if there's things that we dislike, then i back to continue edit board-m101:01
wolfspra1lwhat did plab send you?01:04
cladamwdesign files( I'll check .PcbDoc for placement and their footprint files )01:16
wolfspra1lcan you export and upload a gerber? maybe we can try to compare a little with rc3 using gerbv :-)01:26
cladamwit not gerber files. :-)01:31
GitHub129[board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/eb3de1f8f85fe92647eac401338651070c7fddff02:40
GitHub129[board-m1/master] create empty hierarchical sheet for functional block alike. - Adam Wang02:40
GitHub16[board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/c2a771a66ab954de0518b39f783c81ec37359c0802:46
GitHub16[board-m1/master] added all empty schematics - Adam Wang02:46
cladamw[M1r4] AD version is currently placed under http://downloads.qi-hardware.com/hardware/milkymist_one/pcb/r4/07:19
cladamw[current task] I'm doing the review/confirmation of new pcb footprints.07:21
wpwrakcladamw: how can i view MILKYMISTONE.PCBDOC ?10:13
wpwrak"file" says "CDF V2 Document, No summary info"10:13
wpwrakand libreoffice gives me a very long list of possible choices10:14
cladamwwpwrak, so far i don't know how to let you review directly from .PCBDOC .:)10:17
cladamwit's not completely finished on placement10:18
wpwrakcan AD "print to PDF" this ?10:19
cladamwthe most are for me now is to review/confirm footprint (filename = MILKYMISTONE.PcbLib)10:19
wpwrak(or maybe even "export to gerber" ? :)10:19
cladamwi can export to pdf10:21
cladamwthen you can select part10:21
wpwrakPDF would be great. MILKYMISTONE.PCBDOC has the placement, right ?10:23
cladamwyes, but not initial placement, it just we called "NET-IN" only. :)10:27
cladamw_while NET-IN results from house, i started to review/confirm the footprint via *.PcbLib file, not .PcbDoc10:28
cladamw_this net-in version was house sent to me after one week. so they are still working on the expansion J21/J22 placement, but in this version. It hasn't finished.10:30
cladamw_i'm uploading pdf..moment.10:30
cladamw_[PcbDoc] http://downloads.qi-hardware.com/hardware/milkymist_one/pcb/r4/040912/MILKYMISTONE.pdf10:35
cladamw_Regards to how export *.PcbLib, i don't know at all. But from AD library viewer I can one-by-one to check. It's more the check/detail on comparing datasheet/drawing.10:37
cladamw_[Fped] is the tool to build library. (i.e.)  same house firstly to edit footprint for us. then confirm with us. (this stage as the KiCad of M1r4 to be as review stage as footprint review call)10:41
cladamw_(i.e.) most here what houses are doing.10:42
cladamw_in om, this job were confirmed by layout guy only. not by EE to confirm each footprint, this reason caused many troubles made.10:44
cladamw_wpwrak, I'll go house again since that for placement goal. so if you spot any potential problems, let me know.10:45
wpwrak(no review at OM) heh ;-)10:47
cladamw_wpwrak, liked I said the current pdf genenrated is only for reference. Haven't not drag all parts withing boards. fyi.10:47
wpwrak(looking at the PDF) ah, so that's already a parial laout10:47
cladamw_but the pdf file you can see them. yeah..10:48
wpwrak(not all parts) yes, i can see them on the right ;-)10:48
cladamw_EEs in om were reviewing layout/routings mostly, i almost not see how they review footprints reviews.10:49
cladamw_sorry that i was for PE not EE, not responsible for HW manager can let me worked them. :-) I can head up only. :-)10:50
wpwrak(PE) yuck10:51
cladamw_i just reviewed DVI-I footprint, it's perfect same as datasheet though. :-)10:51
wpwraklooks pretty much like M1rc3 so far10:51
cladamw_few questions: for expansion board10:51
cladamw_1. (height) the relationships between IR.10:52
cladamw_2. J3/J23/J26, they are DNP, and close to the area of expansion board., this is to be done, I'll let house to place sourrounding expansion area. Are you okay ? after that we determine ? or we define them from ourselves firstly ?10:54
wpwrakheight is given by the connectors. i.e., female header + male header, combined height10:55
cladamw_yeah...i knew it.10:55
wpwrakshould usually be something like 10-11 mm10:56
wpwrakthat is, the distance between main PCB and the bottom of the expansion board's PCB10:56
wpwrak(J3 etc.) yes, i'd leave them to the layout house. see what they come up with. they're more like "just in case" anyway. i don't think we should even guarantee that they'll be at the same place in the future10:58
cladamw_total height = J21(female, 8.5mm) + e.g. expansion board thickness (1.6mm) + male header(2.54mm) = 12.64mm , just to confirm that do you have any further placement for IR ? Since the height of IR can be under that area. :-)11:00
cladamw_yeah...so I meant (i.e.) I would let house to move wherever house wants. :-) Do you agree ?11:01
cladamw_so would you do me a favor for drawing the specification for like an "limited height area" under expansion board ? or we do this later after we/house settle the placement done ?11:02
wpwraki would ask the layout people to keep tall parts out of that area in general11:04
wpwrakthen we can define the exact profile based on the final layout11:04
cladamw_ha...that's the guidline one rule but not must. good idea. :-)11:04
wpwrakif they need to put tall parts under the expansion board area, they should be near the edge of that area11:05
cladamw_depends on parts function. :-)11:05
wpwraki.e., i wouldn't want to see a 0.95 mm cap right in the middle :)11:05
wpwrakerr. 9.5 mm11:05
wpwrak0.95 mm would be fine ;-)11:05
cladamw_hehe...yeah..it'll  destroy power of expansion board.11:06
wpwraki think we may overlap a bit with the DVI connector in the lower right corner11:09
wpwrakerr, lower left11:09
wpwrak(lower left of the expansion board)11:09
wpwraksigh. my brain isn't working too well these days :-( enjoying a flu. so if i sound confused, that's why11:10
cladamw_btw, actually the height is 8.5mm + 2.54mm = 11.04mm, a normal pin header's mating length is for example 5.84mm, so J3/J23/J26 can be under expansion area, but it's not good idea for pull out. so i would also let house to place them surrounding area.11:12
wpwrakyes, the best place would be to have them something like 1 mm outside of the expansion board area. that way, one easily make an "extended" board with connectors for them, too11:13
cladamw_(outside 1 mm) okay...11:14
cladamw_(J17) lower left ? sorry can you describe again ?11:14
wpwrak(J17) hmm, looking at it again, it may actually not overlap.11:16
wpwrakyeah. should be clear. false alarm, sorry11:16
cladamw_alright. :-)11:16
cladamw_(U10/U11/U13) power regulators i'll move them lower a bit since we may need to solve the difficulty of current right-angle usb plug doesn't easiler to insert jtag/serial board.11:18
cladamw_which means the routes of current power area may be changed a lot but I leave this to be the last task one. since it means the relationships between jtag/serial board and 8:10 card will be moved a little.11:21
cladamw_but like i said I leave this to be last task, since DVI-I routes are #1. :-)11:21
cladamw_wpwrak, follow me ?11:23
cladamw_wpwrak, i go for dinner first, cu11:26
wpwrakwe give no guarantees with regard to jtag vs. 8:10 anyway11:29
wpwrak(moving jtag) we give no guarantees with regard to jtag vs. 8:10 anyway12:23
wpwrakafk for a few hours now12:29
wpwrakand back again14:35
wolfspraulwpwrak: pah too many things in parallel14:40
wolfsprauldo you have any feedback regarding adam's kicad-m1 work?14:40
wolfspraulI can't keep track of the backlogs right now14:40
wolfspraulit looks like he is charging ahead, looks good...14:41
wolfspraulI upleveled the cmdline patches recently btw, just to stay fit14:41
wolfspraulit's easier to catch the inevitable stream of renames in short bursts than too many lumped together14:41
wpwrakwolfspraul: what he's doing looks good so far. except that he's lumping many components in a single file. that's a structure encouraged by kicad, but it means that the revision control system works poorly14:49
wpwrak(uplevel) yes, saw it. very good, thanks !14:50
wolfspraulwpwrak: so adam should just continue on the current path for now?15:13
Fallenouhttp://pastebin.com/2Nusa0TK < that would explain a few things :)17:39
Fallenoumost of the time it's trying to access page 017:40
Fallenouonly 2 tests are correct !17:40
wpwrakFallenou: hmm, even the addresses with the upper bits the same differ in the lower bits: 0x44002024 - 0x44001024 = 0x100017:53
Fallenouwpwrak: those are correct I was mapping 0x44002000 to 0x44001000  :)19:30
Fallenoudont take my small victory away from me :'19:30
wpwrakah, good :)19:30
Fallenouso now its clear why it crashes  => access to page 019:32
FallenouI need to figure out what timing I have wrong19:32
wpwrak(page 0) ah yes. that explains it nicely19:33
lekernelFallenou: if you want to synthesize faster, you can edit setup.v and disable the cores you don't need19:46
lekernelI see you still have all of them enabled19:47
lekernelif you disable the TMU the BIOS will nicely switch to software scrolling btw19:47
Fallenou21:52 < lekernel> Fallenou: if you want to synthesize faster, you can edit setup.v and disable the cores you don't need < good idea, thanks !20:38
Fallenou8 minutes !20:48
Fallenounice :)20:48
Fallenouinstead of 20/25 min, and still booting bios and running the tests20:51
mwallelekernel: do you think its possible to run the navre core at 72mhz ?21:11
mwallehow would you do it? two clocks? one clock and ce?21:24
lekernelit's already one clock and ce :) keep the same design and just adapt the ce generator21:25
lekernelif you want you can simply CE the CE generaot21:27
lekernelthen going back to 48MHz is just a matter of connecting that CE to 121:28
mwallelekernel: so for the tx side its the gce and for the rx side its the dpll_ce right?21:29
lekernel(of course you need to combinatorially AND the generated CE with the generator's CE)21:29
mwalle(well the ce for the dpll, not the dpll_ce)21:29
lekernelyou can try first to set the DCM to 72MHz and check that it still meets timing21:30
lekernelah, and there's also fs_timeout_counter you need to increase (or CE)21:31
mwallelekernel: mhh is there a way to make 72mhz from 50 with one dcm?21:34
mwallemaybe theres some trick to double the frequency? :) because the synthesizer only allows max multiplication of 3221:35
lekernelyou can use a PLL instead which supports more ratios21:36
mwallemh 400MHz < Vco < 1000MHz21:53
wpwrakwolfspraul: (continue) yes. he's also learning to use the tools, familiarizing himself with some of the quirkier bits, which is good23:16
wolfspraulok, but I want to focus fo finish the transfer asap :-)23:35
wolfspraulalready getting anxious to get the bom going, and maybe even peek into layout - why not...23:35
wolfsprauls/focus fo/focus to/23:36
wpwrakregarding layout, it would be good if we could get what adam has from the layout house so far in gerber. that way, it's possible to help with reviewing the footprints23:39
wpwrakthe PDF alone isn't very convenient for checking geometry23:40
jpbonnI'm trying to use flterm without success.   Is there a pre-built binary I can download and run?23:51
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