#milkymist IRC log for Friday, 2012-04-06

GitHub161[flickernoise] xiangfu pushed 2 new commits to master: http://git.io/qih3Tg04:30
GitHub161[flickernoise/master] remove useless translation: Control panel * - Xiangfu04:30
GitHub161[flickernoise/master] gui/cp.c: break down that cp_notify_changed() - Xiangfu04:30
mwallelekernel: io_do <= io_a, issuing in 0x00 .. in 0x20 returns13:01
mwalle00 01 02 03 04 05 06 07 08 09 10 39 17 13 14 15 16 17 18 19 2013:02
mwalleactually i missed the 0xa..0xf .. lol13:02
mwallereally strange13:03
mwallein simulation i didn't find anything unexpected13:06
GitHub81[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/b9c533be51a7f4a95670ce2a9a89573736e2b7ff13:07
GitHub81[migen/master] bank/csrgen: allow specifying existing CSR interface - Sebastien Bourdeauducq13:07
lekernelmwalle: if there are simulation vs. synthesis mismatches, it could be a case of the blocking assignment causing non-determinism in communications between always blocks13:35
lekernelthe navre source code is full of this gotcha13:35
lekernelwe should clean this up by "buffering" through a non-blocking assignment all signals that are read in another always block13:36
lekerneland, great catch btw. it may help explain some USB bugs...13:36
mwallelekernel: do you know how i can open fst files in gtkwave?13:41
lekernelfst? what's that?13:41
mwallemh, sth like vcd, which can cver export13:42
lekernelcver should support vcd too13:42
lekernelat least the gpl version does13:42
mwallelekernel: 0x1739 <<-- might this be the stack pointer?13:52
mwalleor hte cpu flags?13:52
mwallebtw i did a serial crc5/crc16 checker for the rx path, i'll post the patches on the ml soon. then you can have a look at it and tell me whats all wrong ;)13:55
mwkhey guys13:57
mwkI'm interested in using/developing open source FPGA synthesis tools13:57
mwkI've seen the llhdl/antares efforts, is there anything else?13:58
mwallemwk: there is migen14:27
mwalle00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 19 17 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 3014:27
mwallesth must be special about 0x11 and 0x1214:27
mwalleahhh that the counter, doh!14:31
lekernelmigen isn't actually doing any fpga synthesis. it's a verilog generator.16:25
mwallelekernel: btw do you have a spare usb tranceiver used on the mm?22:10
lekernelmwalle: I think so... what do you want to use that for?22:18
mwallelekernel: add a device port using the expansion pinheader22:18
lekernelmwalle: I have. can send them tomorrow if the post is open in this period of karfreitag, tanzverbot, etc.22:26
lekernelanything else you need?22:26
mwallelekernel: no hurry, atm i'm using a selfmade cable, usb-a usb-a ;)22:26
mwallewith a pullup to 3v322:27
mwallelekernel: i dont think so, i guess these varistors arent really needed, resistors.. i have plenty on work22:30
mwallelekernel: there are no special io requirements for the usb pins, right?22:31
lekernelon the fpga? no22:32
wpwraklekernel: "tanzverbot" sounds like an underground event. are the raves back ? :)22:32
lekernelif only :) http://de.wikipedia.org/wiki/Tanzverbot23:17
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