#milkymist IRC log for Thursday, 2012-03-29

jonandgood morning07:24
jonandI now have the mm rc3 pcb stackup in cadence sigxplorer. Although the layout is very good on the MII bus (no layer changes, good reference to ground plane) it could use a 22 or 33 ohm series resistor07:25
jonandwithout it there is some minor ringing07:26
jonandnot alarming though, it will for sure work good anyway07:26
jonandbut if you guys run into EMI problems this could be a place to start07:26
wolfspraul22 or 33 ohm series resistor where?07:26
jonandon the MII bus between the fpga and the ethernet phy07:27
jonandin the driver ends, that is. 4 at the fpga and 4 at the phy. but as I said, it looks decent anyway.07:28
wolfspraulwhat's your advice? should we change it proactively, or just keep an eye on it / wishlist?07:37
jonandIt really depends on how bad it looks in reality. Did you run the EMI tests with ethernet traffic or are the ethernet + usb ports considered as "service ports" (that do not need testing because they are not connected during normal operation)?07:39
jonandIf a re-layout for some reason means that the MII bus need to switch layer it is a good idea to add the series resistors07:40
jonandI'm trying to run a worst-case (strongest, weakest) model but I and the simulator are not friends today....07:41
jonandany recommendation for a pastebin service for pictures so I can show some screen dumps?07:41
wolfspraulgood question about 'service ports'07:44
wolfspraulwe ran 'typical' use cases07:44
wolfspraulbut they are not properly documented, and the boundary to the 'service ports' is not clear07:44
wolfspraulneither documented nor tested07:44
wolfspraulpastebin for pics, don't know07:45
lekerneljonand: tried changing the fpga io settings (drive strength, slew rate)?07:59
jonandlekernel: I have only tried phy -> fpga so far08:01
jonandlekernel: using the OTERM=25 in your .ucf could probably save you some ringing in the fpga->phy direction08:02
jonandhere is the setup: http://tinypic.com/view.php?pic=w8omr9&s=508:03
jonandand this is what the signals look like08:03
jonandhttp://tinypic.com/view.php?pic=2nl5iy9&s=508:04
jonandnow let's add 22 ohm series termination at the phy: http://tinypic.com/r/inx0mv/508:05
jonandand we get rid of the ringing: http://tinypic.com/view.php?pic=2s0em13&s=508:06
jonandcomparison receiver end before (red) and after (green) adding of series termination: http://tinypic.com/view.php?pic=2wdubg8&s=508:08
jonandas you can see you get a tiny rise/fall time penalty but at 25MHz it's nothing really08:08
jonandmy wet dream are simulations like these in Ki-cad08:09
jonand"how hard can it be?" :)08:09
jonandI really have no clue on how to take ibis (or spice) models, add transmission line (microstrip, stripline and so on) math and feed that output into gnuplot08:13
jonandI just use the commersial tools like black boxes and am happy that what I see in the lab looks very much like what I get from the tools.08:13
jonandBut it would be very cool to get features like this in open tools.08:14
jonandhey, why feed it into gnuplot when you could display it on stage with the milkymist? :D08:16
GitHub98[flickernoise] xiangfu pushed 2 new commits to master: http://git.io/0kEjvg08:23
GitHub98[flickernoise/master] use one PrtScr/SysRq for take screenshot - Xiangfu08:23
GitHub98[flickernoise/master] gui/audio: remove the mic boost ioctl - Xiangfu08:23
lekernelmaybe with this sort of thing? http://www.fastfieldsolvers.com/links.htm08:45
wolfsprauljonand: excellent stuff, thanks a lot!09:15
wolfspraulfeel free to do more simulations, we can't get enough of this stuff :-)09:15
wolfsprauldo we want to add the suggested series terminators?09:16
jonandnot from a functionality point of view. add them if a relayout makes you change layers (the current bus is on top layer only) or if you run into EMI problems while using ethernet.09:26
wolfspraulmakes sense, thanks a lot!09:28
wolfspraulwe are currently debating whether to switch from the current 6-layer to a 8-layer layout09:28
wolfspraulthat's because the new revision R4 introduces some more wires such as digital video (dvi-i combining vga + digital)09:29
wolfspraulso we are not sure whether or how well it can fit into the existing 6-layer layout09:29
wolfspraulwe will know more soon :-)09:29
wpwrak(image upload) how about setting up an account on downloads.qi-hardware.com ? that's convenient for uploads (with rsync or scp)11:41
wpwrakjonand: one limitation we (currently only, i hope) have is that we don't have expensive lab instruments. e.g., the fastest scopes used regularly in the M1/qi-hw universe are 100 MHz DSOs with passive probes. so this sort of ringing would be completely invisible to us by measurement.11:44
wpwrakthis means that we have to rely on (hopefully good) design rules and simulation, with only very coarse feedback (of the pass/fail type)11:47
wpwrakregarding the simulation, this looks like something qucs could handle. we'd have to find a model for the I/Os, though.11:49
wpwrakwhat this model doesn't show are crosstalk and such. would you normally examine these too ? if yes, how would you model them ?11:50
wpwrak(qucs) qucs may not be the best choice for design-driven simulation, though. it seems that spice is both faster and harder to derail. the drawback is of course that spice isn't meant for human users ...11:52
lekernelwpwrak: there are IBIS models published by the various chip vendors, but I don't know how they work internally13:58
jonandYou typically never get spice models from the chip vendors. The reason I've heard is that they reveal too much about the internals of the chip. I guess this is typically a problem for TSMC/UMC/IBM/Toshiba/TI or whatever chip house fabless people are using these days14:03
jonandIBIS models are on the other hand most of the time pretty easy available.14:04
jonandMost IBIS models state in the header "derived from spice bla bla" and if they work at all the simulation results are pretty correct14:04
wpwrakis there a straightforward conversion to spice ?14:05
jonandThat's at least my experience with ~10 models14:05
wpwrakor is there anything in the way IBIS works that would trip spice ?14:05
jonandibis to spice: not that I know of14:05
jonandI've heard that some "top tier" customers require spice models from e.g. Xilinx so that's why they are available for top models like Virtex14:54
jonandI'd say that IBIS is what everyone <500MHz (cycle time) is using. Haven't done any DDR3 myself so I don't know if it is needed.14:55
lekernelhttp://www.youtube.com/watch?v=rSHi5KqjaCk&feature=related 4min+18:42
wpwraklekernel: should be easy to pull off with M1 :)20:24
wpwrak(eispice) unfortunately, it looks a bit abandoned. last release almost 5 years ago. mailing list eerily quiet.21:18
wpwrakof course, the *spice world doesn't seem to be in a great hurry in general. just saw that the spice referenced for ideas in eispice has a manual from 1998. well, i guess nothing really new happened since the transistor ;-)21:26
wpwrakthis one looks more alive: https://github.com/russdill/darter/wiki/Darter---SPICE-based-IBIS-modelling-tool21:27
qi-botThe firmware build was successful, see images here: http://fidelio.qi-hardware.com/~xiangfu/build-milkymist/milkymist-firmware-20120329-2242/22:22
wolfspraulAdam is going to the layout house! :-)23:52
wolfspraullet the games begin23:53
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