#milkymist IRC log for Thursday, 2012-03-08

kristianpaulstekern: hi01:45
kristianpaulHad you noticed i guess the CSR bus detect write cycles from wishbone01:46
kristianpaulI was trying to detect reads too01:46
kristianpaulbut i dont know i guess i did, i met a race condition issue01:46
kristianpaulI was wondering you have some snipets about detecting read and writes cycles from master in wishbone01:48
kristianpaulargh, i will go for writing register to clear flags01:48
kristianpaulbut i wanted clear after read,01:48
kristianpaulwich i still can do, but cheating using unique adress for both reading and writing01:49
kristianpauleven if we talk about same register !01:49
wpwrakif (csr_selected) { if (csr_we) data_reg <= whatever; csr_do <= data_reg; }  ?01:50
wpwrakthat way, you latch the new data with a write cycle and can then quietly read it afterwards01:50
kristianpaulsure, that works with csr_we coming from the csbridge FSM01:50
wpwrakah, and around the "whatever", you can also clear and so on01:51
kristianpaulyes but when writing (csr_we)01:52
kristianpaulthere is no csr_re for instance01:53
wpwrakno, there's not :)01:53
wpwrakbut why do you want to do it all in one cycle ? do you have performance problems ?01:53
wpwraki.e., no time for two cycles ?01:53
kristianpaulsure i could two cycles01:54
kristianpauli just dont want break register compliance against namuru upstream01:54
kristianpaullater Artyom code,,, erghh and others01:54
kristianpaulbut i wanted to clean up things a bit :)01:54
kristianpaulat least !01:54
kristianpaulbut no no more01:55
wpwrak(compatbility) ah, that's why !01:55
kristianpauland noticed this dint changed on migen, perhaps is milkymist way to go and i should break compatbility anyway02:00
wpwrakyou can always worry about that later :)02:02
kristianpaulyes yes, i _know_ but i cant, argh02:02
kristianpaulanyway !02:02
kristianpauli would worry02:02
kristianpaulseems thats the rule..02:03
wpwrakit helps you to avoid getting stuck on a problem for which you may find a better/easier solution later, without much effort02:07
Action: kristianpaul stuck02:08
kristianpaulThanks werner !02:08
kristianpauland gn8 ;)02:08
stekernkristianpaul: I'm not sure I understand the problem you are trying to solve, but to answer the question. in wishbone you detect a read cycle by stb & cyc & !we03:28
stekernso I guess for CSR you've got to do csr_selected & !we to detect a read03:35
larscyou can't detect read cycles with CSR. You should always output the register value whenever csr_selected is true09:15
wpwraklarsc: i wonder what would happen if someone implemented stekern's idea. multiple read "strobes" in a single cycle ? stray "strobes" when not even reading ?11:32
wpwraki.e., we keep on telling people it's wrong, but we don't tell them why it wouldn't work11:33
larscwpwrak: well, it's undefined behaviour.11:41
larscthe problem is that we don't have any strobe signal at all11:41
larsci think with the current implementation csr_selected & !we is true for multiple cycles11:42
larscnot sure about the milkymist-ng implementation though11:43
lekernelmodify on read is evil anyway11:44
larscbasically you can't support any operations on a CSR bus which are not idempotent. doesn't matter whether it is read or write11:48
wpwraklarsc: wait ... are you saying that we don't have a write strobe either ? i.e., if (csr_selected && csr_we) count <= count+1;   wouldn't work as expected ?13:33
lekernelwpwrak: we do have a write strobe, and that would work as expected13:42
wpwraklekernel: phew :-) thanks13:47
wpwraklekernel: so what would happen in stekern's example ? would you just get multiple "strobes" per read ? or also "strobes" when there's no read ?13:48
lekernelyou can get both multiple "read strobes" or stray ones13:49
lekernelwhen !csr_we & csr_selected, you are required to output valid data at all times, but there's no way to know if there was a legitimate read or not13:50
wpwrakokay. so it's as bad as possible. good. this should discourage everyone ;-)13:51
lekernelwell it's meant to be used with actual _registers_13:51
lekernelthe read implementation is just 1 mux + 1 FF13:52
lekernelyou can hardly do any simpler13:52
wpwrakyeah :) it's a trap for people trying to implement something fifo-like, though.13:53
larsclekernel: your csr spec doesn't really specify that a the we signal must only be asserted for one cycle13:53
wpwrak(well, until they learn how it works :)13:53
lekernellarsc: then it should :)13:53
larsclekernel: ok13:54
lekernelbut iirc it does say that all accesses complete in one cycle, and if you have two we assertions, you have two cycles ...13:54
larsci thought that too, but couldn't find it in the spec13:55
larscmaybe it's in your thesis?13:56
lekernelhmm... not sure... anyway, it's in the IRC logs now =]13:56
kristianpaul true for multiple cycles, yes14:04
kristianpauli was looking at uart core from lattice micosystem, it uses a separte always block with a sensitive list for we stb cyc14:05
kristianpauland read both write and read strobes.. okay this could get worse, oh messy could get . :-|14:06
kristianpaulokay, interesting disccusion :-)14:09
kristianpaulThanks for your  feedback!!14:09
lekernelkristianpaul: anyway, the 'bank' module in migen generates this sort of things automatically now. you'll probably like it, since you are so lazy.14:20
Action: kristianpaul so lazy14:24
kristianpauleven for trying migen now ;)14:24
GitHub107[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/decbd069fafcbb59cadc3672fa479c3ac2ff9cbc14:34
GitHub107[migen/master] sim: fix message debug formatting - Sebastien Bourdeauducq14:34
stekernaha, I see there is no "none-selected". but what's the problem anyway, if you need some more complex functionality, just hook it straight up to the wb-bus then?14:57
lekernelnice: when you pass a pointer to vpi_put_value (which you do when writing more than 32 bits), the simulator only reads that pointer after the specified delay15:27
lekerneland it seems there's no way to specify a "free()" callback15:27
lekernelso... the usual round of bugs... when allocating that pointer on the stack, it intermittently writes garbage, if you reuse the structure, several signals get the same value when they should not, etc.15:28
lekernelguess it would have been too simple to let the simulator copy memory ...15:30
lekernelfortunately I only have delta delays here, so if I can't find anything better I'll just keep a linked list of malloc'd buffers to free at the next cycle ...15:32
larscsounds like a lot of fun15:35
lekernelgrmbl... in fact as per the VPI standard you can have a callback, but icarus verilog doesn't support it15:44
lekernelahem... https://github.com/steveicarus/iverilog/blob/master/vvp/vpi_priv.cc#L101115:48
lekernelpatch sent :)16:28
GitHub169[migen] sbourdeauducq pushed 3 new commits to master: https://github.com/milkymist/migen/compare/decbd06...ddc0e4916:34
GitHub169[migen/master] sim: fix zero encoding - Sebastien Bourdeauducq16:34
GitHub169[migen/master] examples: small cleanup - Sebastien Bourdeauducq16:34
GitHub169[migen/master] vpi: patch for Icarus Verilog - Sebastien Bourdeauducq16:34
GitHub80[migen] sbourdeauducq pushed 3 new commits to master: https://github.com/milkymist/migen/compare/ddc0e49...84aa70317:21
GitHub80[migen/master] bus: generic transaction model - Sebastien Bourdeauducq17:21
GitHub80[migen/master] gitignore: update - Sebastien Bourdeauducq17:21
GitHub80[migen/master] vpi: support extra include directories - Sebastien Bourdeauducq17:21
GitHub143[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/f4adb0fe9c2b41e03688708971d49a6bc9c09dce17:24
GitHub143[migen/master] examples: remove outdated wb_intercon simulation - Sebastien Bourdeauducq17:24
kristianpaulargh icarus have troubles detecting a module instasciation...19:37
GitHub176[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/f4adb0f...57a87b319:56
GitHub176[migen/master] fhdl: handle negative constants correctly - Sebastien Bourdeauducq19:56
GitHub176[migen/master] examples: FIR filter simulation - Sebastien Bourdeauducq19:56
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