#milkymist IRC log for Sunday, 2012-02-19

wolfspraulwpwrak: very cool wheel video! :-)00:24
hypermodernThank you lekernel00:43
Action: fpgaminer is wondering how useful a ring oscillator based temperature sensor would be in preventing chip damage on a Spartan-6...08:03
Action: fpgaminer waves08:35
lekernelfpgaminer: it would work - but do you really make the chips so hot?09:35
lekernel(of course, assuming you compensate for process and voltage effects too)09:36
fpgaminerlekernel: You bet. Without a heatsink the mining firmware will easily cook the FPGA.10:34
fpgaminerWhich is great for BBQs but ... not so great for making Bitcoins :P10:35
lekernelwhat do you have in there which uses so much power?10:53
lekernelhave you tried using XPA?10:55
fpgaminerlekernel: 200MHz, >75% slices occupied on an LX150, and a high toggle rate.11:03
lekernelFallenou: iirc mvhi sets the 16 LSBs of the register to 014:29
Fallenouoh really ?14:30
Action: Fallenou checks14:30
Fallenouoh yes14:30
Fallenouyou're right14:30
Fallenouit means I don't have to xor the register14:31
larscmvhi is just orhi with r014:34
lekernel"Additionally, the use of local routes within the CMT provides an improved clock path because the route is handled locally, reducing chances for noise coupling."14:36
lekernelnoise coupling inside the fpga... sounds nice14:37
Fallenouwhat is CMT ?14:43
lekernelthe tiles in S6 FPGAs which contain DCMs and PLLs14:44
Fallenouare they only located on the edges ? or inside too ?14:45
lekernelhttp://www.xilinx.com/support/answers/46141.htm <= I really wonder if NWL really got their PHY to work, since it uses CLKOUT3 with a 90 degree shift14:55
larscwell, if it only happens in 13.415:01
lekernelno, no, read it well... 13.4 _and earlier software_15:02
lekernelwhich means it never worked15:02
Fallenoubut since it's software it means they will be able to correct it for 13.5 :)15:02
larscok, missed the "and earlier"15:02
Fallenoumaybe it can be corrected with planahead post processing on the bitstream ?15:03
lekernelmaybe, but it doesn't explain how NWL released that PHY oh, one year ago?15:03
lekernelwith that bug and no one noticed15:03
Fallenoumaybe they just don't need the phase shifting15:03
lekernelthey do need the phase shifting15:03
Fallenouok ^^15:03
lekernelit's necessary for generating critical DRAM control signals15:04
Fallenouwell on the xilinx support page they say "may/can" so maybe in this precise case it does not happen (the bug)15:04
Fallenouit does not seem to happen 100% of the time15:04
lekernelthat, the DQS problem with DDR1, and the calibration FSM not working (I haven't fully investigated this last bug)... ahem15:05
Fallenoudo you know someone using it ?15:05
lekernelthe PHY was also tickling a MAP bug that made the placement of the BUFPLL fail, but I don't know if it was a ISE regression or just another thing that NWL didn't test15:06
lekernelas usual, DRAM + FPGA = complete mess ...15:06
lekernelno matter how much "IP" they throw at it, they seem to always get it wrong somehow15:07
lekernelDDR4 will be fantastic15:08
Fallenoudon't they have "hard" ddr ip controller inside fpga ?15:09
Fallenouwhich could work15:09
lekernelthey do, but it has a bunch of problems too15:10
lekernelthey even removed it from the -7 series15:10
lekernel"naaaah, no more hard DRAM controller PLEAAASE!"15:10
Fallenoutoo bad SRAM is that expensive15:11
Fallenou'cause DRAM seems to be a real mess15:11
lekerneloh, I'm sure that fast SRAM (QDR etc.) and this kind of high-quality timing generation can lead to funny things too15:12
lekernelbut yes, the control algorithm is much simpler. it's a different problem though.15:12
Fallenoudoes "ddr controller chip" exist ?15:13
lekernelon PCs, it's usually part of the motherboard "northbridge" chip... but it also tends to be integrated with the CPU those days15:14
Fallenouyep with sandy bridge stuff15:14
lekernelit's pretty large stuff... http://en.wikipedia.org/wiki/File:IBM_T42_Motherboard_IMG_2591a.jpg15:15
lekernelalso, multiplying the number of chips in the memory path increases latency15:17
Fallenouyes sure15:17
Fallenouthey have a DDR2 demo on digilentinc Atlys board15:21
FallenouI wonder which ddr controller they use15:21
FallenouLattice also released a SDRAM controller (both vhdl/verilog code) with testbench and documentation15:27
Fallenoubut their license is not clear15:27
lekernelSDR and FSM with auto-precharge... that's a very simple one :) we already have a faster one...15:40
lekernelwhat I'm trying to do atm is (1) run the SDRAM command bus at twice the system clock frequency (and the data four times faster the system clock) (2) process two requests at once (3) reorder requests15:42
lekernel#1 is causing problems atm due to PHY and toolchain bugs15:43
Action: kristianpaul tought new PHY was fore getting faster memory16:41
kristianpaulFallenou: seems license stick its use to lattice products16:48
Hodappw00t. I had Staples print out the thesis paper for the Milkymist, should be ready soon...16:49
Hodappbeen very intrigued but my tablet is a little small to read a 100-page paper on16:50
GitHub32[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/1b8cb5b46ce7228eab43141ff8810afab7bd432217:03
GitHub32[migen/master] bus/dfi: fix multiphase naming - Sebastien Bourdeauducq17:03
lekernelkristianpaul: all the new PHY is supposed to do is sort out timing issues to get the SDRAM base clock at 2x the system clock17:03
lekernelthis would only get a 2x increase in memory bandwidth, but I'm also planning a more powerful controller17:04
kristianpaulthe PHY also deal with crossing clock domain issues?17:06
kristianpaullekernel: what about for FML, it will be use same clock domain fro the PHY or?17:08
lekernelthere won't be FML anymore17:08
kristianpaulno need?17:08
lekernelFML doesn't support transaction reordering17:08
kristianpaulergh, so the TMU will share bus with others cores?17:10
Action: kristianpaul click17:10
kristianpaulbtw any plans to support a wishbone switch-like bus with migen? :-)17:11
lekernelit's already there17:12
lekerneland it works17:12
kristianpauli need check that17:13
lekernelthat's all. migen automatically builds the interconnect based on this.17:14
kristianpaulso it decides wich logic is better shared bus or a mix switch-like wishbone implementations?17:15
kristianpaulI dont disgree with sofyware generaring software but i need understand this better before give it a bite17:15
kristianpaulbut i havent forget i want namuru be happy with migen/milkymist-ng ;-)17:16
lekernelno you define this manually17:16
lekernelInterconnectShared is just a shortcut for arbiter -> shared bus -> decoder17:16
kristianpaulyeah, that is messy by hand17:17
kristianpaulof course best looking code ;)17:17
kristianpauli dont see a class for a Cross Bar Switch Internconnect..17:19
kristianpaulmay be i missudertand you at first17:19
lekernelthere isn't any, but you can build it easily from the arbiter and decoder classes17:19
kristianpaulahh ;-)17:19
lekernelit doesn't make sense to have a xbar on MM, most transfers are with the memory17:20
kristianpaulbut you implemented it some time ago it was with NOR17:21
lekerneland I have already enough to do with the things that make sense *g*17:21
kristianpaulyeah memory17:21
lekernelno, it wasn't really xbar17:21
kristianpaulwhat was it then?17:21
lekernelwell, it was a partial xbar17:21
lekerneland it's no longer needed, it was to try to fix some issues with ethernet DMA from the BIOS17:22
lekernelbut we no longer have DMA for ethernet17:22
kristianpaulwhat i like most of migen is this top.py for milkymist-ng17:23
kristianpaullooks prerry simple :)17:23
lekernelhe, if you want DMA, you know what to do right? :-)17:23
kristianpaulask you  first? ;-)17:24
kristianpaulmay be you reconsider, lol17:24
kristianpaulbut no i dont need, i prefer do the heavy memory stuff on the core, and dont disturb the rest of the SoC17:25
kristianpauli guess that was the buggy part with minimac at first..17:25
kristianpaulnot saying i was memory corruption somehow.. ;)17:26
lekernelthere were multiple bugs, but the most annoying of them was that the FIFOs were becoming very large in attempt to prevent under/overflows17:26
lekernelso now it's storing whole packets in block RAM, which is much simpler, and does not waste my time17:27
kristianpaulindeed :)17:27
kristianpauland since block RAM seems to me more abudant in xilinx-7 devices well :)17:27
lekernelbut if you want to implement DMA, I can recommend you to keep storing the whole packets in BRAM instead of fighting with overflow issues17:28
lekernelwith the block RAM, it should be pretty simple to do, in fact17:28
lekerneljust a small FSM17:28
kristianpaulyes i do follow that recomendation17:28
GitHub62[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/usww_Q17:49
GitHub62[milkymist-ng/master] Prepare for new DDR PHY - Sebastien Bourdeauducq17:49
kristianpaullekernel: what you think of a phisical connector that wires to milkymist wishbone bus, with some aid from bios and a control logic (tree state stuff) it could allow to plug wishbone compatible boards, dont yout think?18:26
kristianpaulmwalle: where  i write system frequency? is flash or hardcoded to bistream?18:46
kristianpaulanyway, this means bios adapt it self to system clock freq?18:46
bkerowin 2718:47
kristianpaulah yes sysctl18:48
lekernelwishbone is just too many wires18:53
kristianpaulah, yes i forgot there is bidireccional buses..18:54
kristianpaulargh, xst dont matters this kkjj|  .sys_clk(sys_clk)19:04
kristianpauli wonder that it think it was..19:04
kristianpaul"kkjj|  .sys_clk(sys_clk)" <--  this19:05
Fallenoukristianpaul: why bios would need to know system frequency ?19:11
kristianpaulFallenou: it does ! it reads from a CSR register19:14
kristianpaulcommit b9605012ac9554645386e192db5f6cc4b67aefe119:14
kristianpaulit seems adjust timers19:14
kristianpaulso uart can work correctly?19:14
Fallenouoh for timers ok19:15
Fallenouuart does not need to know freq at bios level iirc19:15
Fallenoufreq is in hard in the hdl19:15
kristianpaulah yes19:15
kristianpaulthat it is right !19:15
kristianpaulso what are timers for? :)19:15
Fallenoudunno ! for whatever you want :p19:16
kristianpaulFallenou: https://gist.github.com/186526019:17
kristianpaulseems gdb uarts was the excuse CSR_UART_DIVISOR :-)19:19
kristianpaulisnt mwalle ?19:19
lekernel[{#«#{(!! I managed to make a design that fails timing in PAR but the timing analyzer reports no problem19:31
kristianpaulgood you alredy know to to cheap xilinx tools ;-)19:33
kristianpauls/to to /how to19:33
GitHub15[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/DYYWVQ19:55
GitHub15[milkymist-ng/master] s6ddrphy: clock, address and command - Sebastien Bourdeauducq19:55
--- Mon Feb 20 201200:00

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