#milkymist IRC log for Thursday, 2012-02-16

wpwrakgrmbl. most of github is down :-(00:42
whitequarkthey're under DDoS00:42
whitequarkwhat kind of person would DoS a site like github?!00:42
whitequarkI've heard that someone hosts their static pages on github and their site is under attack, through00:42
whitequarkhttps://status.github.com/00:42
whitequarkah00:43
whitequarknot ddos anymore00:43
wpwrak"unicorns" :)00:45
whitequarkerm00:48
whitequarkyou know what preforked Apache is, right?00:49
whitequarkthis is called "unicorn" in Ruby/Rails world by some reason (mainly the weird sense of humor of the author)00:49
whitequarksomehow rubyists often think that stupid names like "libpng" are too boring00:50
whitequarkand they call libxml "Nokogiri"00:50
whitequark(that's a libxml binding, not a clone of course.)00:50
whitequarkactually, nokogiri means "saw" in Japanese (the metal thingy, that is), but good luck determining the function of the package from its name.00:51
whitequarkpersonally, I prefer these kinds of names by two reasons: 1) easier to google 2) similar things don't get called by similar names, and hence there is less confusion.00:52
whitequarka preforked server for slow clients is called "Rainbows!". yes, exactly like that, with the bang symbol at the end.00:53
kristianpaulxiangfu: thanks i'll try out03:10
xiangfukristianpaul, nope :)03:16
cladamwaseems using tiny voltages changed between ground contact and cable shield is worth paying attention to capture action of insertion/removal but probably not in M1 case. With this tech, it should be more applied in measurement industries.04:09
Fallenouhttp://downloads.qi-hardware.com/hardware/milkymist_one/sch/tmp/MILKYMISTONE.pdf < red cross means "not connected" pin ? shouldn't we ground them instead of nc ?09:34
wpwrakCONNECTED AGAIN !!! ;-))13:20
GitHub64[flickernoise] wpwrak pushed 1 new commit to imaginarium: http://git.io/mZARug13:20
GitHub64[flickernoise/imaginarium] images: make images array variable - Werner Almesberger13:20
wolfspraulwpwrak: what happened?13:21
wpwrakseems that one of the building's infrastructure power lines failed. elevators were down, too.13:22
wolfsprauloh13:23
wolfspraulso you had to climb 13 floors?13:23
wpwraknaw. i didn't run out of any urgent supplies :)13:24
wolfspraulah good :-)13:24
wolfspraulyou were worried that my pcb core idea would fail over expensive copper, so I checked13:24
wpwraki just checked the elevators to know the general status of the infrastructure. to ask the janitor, i would have had to climb those 14 floors ...13:25
wpwrakand ?13:25
wolfspraulprice of a 50x60cm core is 5-11 USD depending on thickness13:25
wolfspraulroughly13:25
wolfspraulsay 5 USD for a 0.3mm core, then 11 USD for 3mm13:25
wpwrakand the same in 3 mm acrylic ?13:25
wolfspraulcopper makes no big difference at all, so the range is still 5-11 USD13:25
wpwrakah, interesting13:25
wolfspraulone by one. pcb makers don't know much about acrylic :-)13:25
wpwrakso they throw in all the chemistry "for free"13:26
wolfspraulthere must be a difference, of course. but I would only be able to find it out if I negotiated hard prices for larger volumes, which is too tiring just for the heck of it.13:26
wolfspraulsay for 1000 50x60 panels - I'm sure there will be a difference whether I want copper or not, and how thick the copper is, etc.13:27
wolfspraulbut if I just buy 1, it's the same 10-11 USD for 2.5mm or 3mm, with or without copper13:27
wolfsprauljust fyi13:27
wolfspraulmy feeling is that the copper part must be < 1 USD (of those 11)13:27
wpwraknot a bad price. at one of the local shops, the same amount of acrylic (unprocessed) would be around USD 1813:28
lekernelBUFIO2 #(13:56
lekernel      .DIVIDE            (1),                       // The DIVCLK divider divide-by value; default 113:56
lekernel      .DIVIDE_BYPASS    ("FALSE"),13:56
lekernel      .I_INVERT         ("FALSE"))                // I_INVERT attribute to be added in last week of jan 200913:56
lekernel...13:56
lekernelthe DDR PHY clocking is such a mess13:56
wpwrakit's like a christmas present. it brings bad luck if you open it before the 24th ;-)14:22
lekernelthis thing requires no fewer than 10 different clock signals14:25
lekernelwith various phase/frequency relationships and FPGA routing restrictions14:26
lekernelhttp://elmelectronics.com/ebench.html#ELM46014:30
wpwrakcomplexity keeps your job safe :-)14:33
wpwraklekernel: i'm looking for a place to put things like the pacman, the heavily midified tornado, etc. these are code examples that illustrate how things work but they may not be readily usable like the rest of the patches14:36
wpwraklekernel: i'd still like to keep them in flickernoise.git, to keep them synchronized with the rest.14:37
wpwraklekernel: what i wouldn't want to happen is that they end up in a web update by accident14:37
wpwraklekernel: would (a) subdirector(y|ies) in patches/ be safe ?14:37
lekernelyeah, the webupdate patches are handpicked atm anyway14:38
wpwrakoh, perfect :) thanks !14:38
wpwrakit seems to be surprisingly difficult to get the frame number wrap around the maximum. somewhere, there's something very weird going on ...14:51
wpwrak(and no, i'm not using % ;-)14:52
lekernelwhoa! it synthesized!16:57
lekerneland without complaining dozens of times about unroutable clocks after 20 minutes of runtime at each attempt16:58
lekernelit even works (or at least, the 1x clock does and all the PLLs lock). great!17:05
GitHub14[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/c08687b9c6032c4236c413ec32c52c4a481901a117:07
GitHub14[migen/master] bus/dfi: filter signals by direction - Sebastien Bourdeauducq17:07
GitHub53[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/nY3Jfg17:08
GitHub53[milkymist-ng/master] Generate all clocks for the DDR PHY - Sebastien Bourdeauducq17:08
kristianpaulgood !, free IP cores seems to be usefull after all ;)17:27
HodappI hadn't realized Milkymist was semi-compatible with MilkDrop... maybe if I'd ever have used the latter or read the thesis paper it would have helped17:38
GitHub187[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/ca7056b07fb90b9424fa33918b5d701577e23be917:40
GitHub187[migen/master] fhdl: support forwarding of bidirectional signals from instance ports - Sebastien Bourdeauducq17:40
GitHub141[milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/4FS_wg17:41
GitHub141[milkymist-ng/master] lm32: compatibility with the new instance API - Sebastien Bourdeauducq17:41
GitHub141[milkymist-ng/master] m1crg: make clock feedback pin bidirectional - Sebastien Bourdeauducq17:41
wpwrakHodapp: we have a the option of using a nicer syntax, though17:58
wpwrakHodapp: milkdrop syntax is kinda evil :)17:58
lekernelhmm... if I make all accesses to a single page of DRAM and keep that page open, I should not need to refresh, right?18:17
lekernel(of course, this will destroy the data in the other pages)18:17
lekernelI'm thinking about the simplest way to do the startup calibration of I/Os ...18:18
lekerneldriving the DRAM pins directly from a software routine (like the initialization sequence is done) sounds interesting, but refreshes might complicate things a bit18:19
Fallenou(mmu) if someone has an idea on this problem : http://pastebin.com/frQR9FWj18:22
Fallenouit seems incoherent, what I see in simulation, with the verilog code18:23
Fallenouthis is the source of my problems, leading to d_dat_o and d_adr_o of lm32 being XXX when doing a memory store18:24
lekernelFallenou: is that your modified source? did you get the original to work 100% correctly?18:25
Fallenouyes it's the modified one, but here I'm in kernel mode18:26
Fallenouso in theory nothing is modified18:26
FallenouI should try with totallyunmodified lm3218:26
FallenouI honestly never tried memory stores with unmodified lm32, only memory loads18:27
Fallenoubut modified or not, it's strange that the value is incoherent, or I missed something ...18:28
lekernelit's probably going to be easier to track if you have a working version18:28
larscno other drivers for operand_w?18:28
Fallenouresearch in vim only gives me those "two" drivers18:28
Fallenouwhich is one actually because of the `ifdef18:28
larscand to be sure that the simulator is not stumbling upon the ifdef I'd remove the second18:29
Fallenouand the 3rd for reset condition18:29
Fallenouoh yes good idea18:29
Fallenoustill the same thing18:31
FallenouI commented ifdef, else and the unused driver18:31
Fallenouand endif18:31
GitHub168[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/TejZeg18:35
GitHub168[milkymist-ng/master] clkfx: remove - Sebastien Bourdeauducq18:35
FallenouI get the same thing with almost unmodified lm3218:42
Fallenouhttp://pastebin.com/5jKuDGtC18:42
Fallenouonly this is modified18:42
Fallenouit's necessary to get simulation "compile"18:43
Fallenouotherwise it does not even "compile"18:43
lekernelha, and how do you initialize r0?18:56
lekernelbe careful, in verilog X ^ X = X (not 0)18:57
lekernelthough X ^ X = 0 on the hardware, assuming it's the same signal18:57
lekernelone of many discrepancies ...18:57
FallenouI do xor r0, r0, r018:57
lekernelyes, so it won't work18:58
Fallenouwell I hoped that my ram[0] = 0 would at least initialize r0 to 018:58
Fallenouin lm32_dp_ram.v18:58
lekerneldon't do such hacks... get the original code to work18:58
Fallenouis there a way to 0 a register ? other than xor rn, rn, rn ?18:59
lekerneljust reset the register file with an initial statement in simulation18:59
lekernelwhat's the problem with the code you commented out?19:00
FallenouERROR:HDLCompiler:69 - "lm32_cpu.v" Line 2781: <reg_0.mem[0]> is not declared.19:01
FallenouERROR:HDLCompiler:69 - "lm32_cpu.v" Line 2782: <reg_1.mem[0]> is not declared.19:01
FallenouERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed19:01
whitequarklekernel: err what. X ^ X = X ? why?19:02
Fallenoumaybe I should put .ram instead of .mem19:02
lekernelwhitequark: because verilog is crap19:04
whitequarklekernel: not an answer19:04
lekernelthere's even worse, 0*X=X19:05
FallenouX means "undefined" in verilog19:05
Fallenouso they just say undefined xor undefined = undefined19:06
Fallenouit ends up stupid with for example a ^ a != 0 if a == X19:06
whitequarkahhh, I got it. you don't mean X as a variable19:06
Fallenounop19:07
FallenouX is the value19:07
Fallenou0,1,X,Z19:07
whitequarkyeah, then it's logical19:07
Fallenoulekernel: registers seems to be reseted to 0 be the reset condition19:08
lekernelwhat would have been logical is to remove X from the language - it causes more problems than it solves19:08
Fallenousee line 2668 of lm32_cpu.v19:08
lekernelbut do you have LM32_EBR_REGISTER_FILE ?19:11
lekernelit seems so, since it executes reg_0.mem[0] ... statements?19:11
Fallenouyes I think we don't use at all the reg "registers"19:11
Fallenouwe use the lm32_dp_ram instead19:11
Fallenounow it compiles, with .ram[0] instead of .mem[0]19:12
Fallenoubut it still bugs19:12
Fallenousame problem19:12
Fallenouoh, but I only initialize r019:13
FallenouI should initialize all registers I guess19:13
Fallenoulekernel larsc < OK, perfect, thanks19:20
Fallenouhttp://pastebin.com/CJuHgcNd < I added this to lm32_dp_ram.v19:21
Fallenouworks nicely now :)19:21
lekernelcool19:32
lekernelyeah, X is nasty. there are even complete papers and presentations written on this mundane and annoying topic19:33
lekernelhttp://www.arm.com/files/pdf/Verilog_X_Bugs.pdf19:33
lekernelfor example ...19:33
lekernelI guess it gives Verilog coders more job security19:34
Fallenouahah19:34
Fallenouit made all the red signals of my simulation disappear19:35
Fallenoumagic initialization19:35
Fallenou\o/19:35
Fallenouand mmu stores seem to work as well (at least in simulation)19:40
larscFallenou: nice :)21:16
lekernel_are there any DDR1 memories with differential DQS?21:39
lekernel_that supposedly DDR1-compatible PHY has hardcoded differential buffers for DQS, but afaik all DDR1 memories have single ended DQS21:40
lekernel_[{#~#{! that crap won't also generate the correct number of serdes I/O buffers21:58
lekernel_I guess it is safe to assume it has never been tested with DDR1 and with a data width different from what is installed on NWL's devboard ...21:59
lekernel_ha! now, of course, those 'unroutable clock' errors that I mentioned earlier and friends are coming in23:07
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