#milkymist IRC log for Tuesday, 2012-02-07

kristianpaulha, Virtex-7 dev kits prices are un-reacheable for us poor :-)02:19
kristianpauls/Virtex-7/Xilinx 702:19
Action: fpgaminer is waiting for a Kintex-7 devkit02:23
Action: fpgaminer maybe02:23
Action: fpgaminer so he can pine and wishes he had the money02:23
kristianpaulfpgaminer: Hi !02:23
fpgaminerkristianpaul: Hello!02:23
kristianpauli havent seen you since months !02:23
kristianpaulfpgaminer: do you still using chipscope for comunicating with your miner core?02:24
fpgaminerYeah, I've been trying to earn my wages! :P02:24
fpgaminerkristianpaul: No, I moved on to using the JTAG core directly. :P02:25
kristianpaulwhat commit was that.. let me update02:25
wolfspraulfpgaminer: hi there! ;-)02:25
fpgaminerwolfspraul: Hey :)02:26
Action: wolfspraul fpgaminder and self had some really inspiring private mail exchanges about Milkymist lately - thanks!02:26
wolfsprauland... fpgaminer is much more than just about (bitcoin) mining - the nick is misleading...02:26
kristianpauli was checking ztex miner core, and wondering if it relly on external MCU for real mining02:26
kristianpaulwas it pragmatic soemthing?  (nick) :-)02:27
fpgaminerkristianpaul: I think it was back in Aug/Sep. I added it to the LX150_makomk_speed_Test variation.02:27
fpgaminerwolfspraul: Yeah, I hope I can help with the DVI/HDMI development in some way :) Like I said, I'll keep my eye on the mailing list02:28
kristianpaulfpgaminer: can you tell us a bit how to you end coding tha open source fpga miner? i read there was a common effort then break in many forks, so what you based your code on?02:28
kristianpaulC code? all from scratch?02:28
fpgaminerkristianpaul: I built my code from scratch after learning up how the algorithms worked02:29
fpgaminerkristianpaul: Then I published it on github and the Bitcoin forums and others jumped on to help improve it and port to other platforms02:29
kristianpaulnice !02:30
wolfspraulfpgaminer: the next board spin (called R4) will switch from our current VGA connector to a DVI-I connector02:30
wolfspraulso it will leave the analog path as-is (to keep the product functioning), and add new digital wires that are going directly into the fpga02:30
wolfspraulquite risky, a lot of unknowns for us in that02:30
wolfspraullike we have to route those wires all over the board to not disrupt the current layout, pin assignments, and so forth02:30
wolfspraulwe also want to stick with our 6-layer board and not go to 8-layer just for those wires02:31
fpgaminerwolfspraul: As long as the AC characteristics are within the DVI spec, and they're routed to the right pins on the FPGA, you shouldn't have any issues.02:31
kristianpaulfpgaminer: i noticed you are experimenting with lm32 latelly ! :)02:31
wolfspraulthe actual implementation of supporting HDMI will probably (I would think) use the migen stuff Sebastien is working on now (?)02:31
wolfspraulfpgaminer: good. If you can look over some of that at some point (schematics and partial layout), we would all take a deep sigh of relief here ;-))02:32
wolfspraulgive it a few more weeks then it should be fully designed (sch+layout)02:32
wolfspraulit's moving...02:33
fpgaminerwolfspraul: I certainly will, though I don't normally deal with the schematic layer of DVI/HDMI02:33
fpgaminerkristianpaul: Yup, all thanks to Milkymist!02:33
kristianpaulsee that lekernel ! ;-)02:33
fpgaminerkristianpaul: I've actually got ethernet working now :D02:33
kristianpaulYou must be proud :-D02:34
fpgaminerkristianpaul: Now I'm just fighting RTEMS compilation so I can get that running. It really does _not_ like compiling on Windows.02:34
kristianpauloh, you tried :)02:34
wolfspraultry a Linux virtual machine on Windows? ;-)02:35
wolfspraulthat's just a big app, no?02:35
fpgaminerYeah, I've more or less given up on a Windows compilation for now and just booted up Ubuntu in Virtualbox02:36
kristianpaulJTAG Atlantic core, what is that a IP thing?02:36
fpgaminerI can get the cross compilers to compile on Windows, but RTEMS throws up. Apparently Cygwin has some nasty fork bugs on Windows 7 64-bit.02:36
kristianpaulfpgaminer: so you dint like the idea of serializing data for reading/writing a miner core, or what lead you to implement the jtag interface?02:37
kristianpaulalso i think i'll try your core soon my M1's lx45 fpga, as it seems can fit on  it well ;)02:38
kristianpauli had been reading bitcointalk forums latelly02:38
fpgaminerkristianpaul: Yeah JTAG Atlatnic is an Altera IP; JTAG-UART bridge. It's their only JTAG core that you can access from C/C++.02:38
kristianpaultrying to find a clean miner core base02:38
kristianpaulI see02:38
fpgaminerkristianpaul: I use the JTAG interface for development, because it means less wires running to the dev board :P And for production, it means a simple and cheap board.02:39
fpgaminerkristianpaul: The DE2_115_makomk_serial folder uses a UART for communication if you're looking for that. It's probably easy to port to Xilinx.02:41
kristianpaullooks similar to Icarus (from the module input output naming)02:42
kristianpaulalso some parameters..02:42
fpgaminerDoesn't Icarus use my core?02:42
kristianpaulYES !02:43
fpgaminerI think ZTEX was the only one to use his own code02:43
kristianpaulha ihavent looked at that folder of your before, too many ;)02:43
fpgaminerkristianpaul: Yeah, I have a lot of variations for such a small codebase :P02:43
kristianpaulif do LOOP_LOG2 bigger the core will use less resources?02:45
fpgaminerLOOP_LOG2_CONFIG cuts the pipeline in half per increment02:47
fpgaminerso LOOP_LOG2_CONFIG=0 will fully unroll the pipeline and use the most resources02:47
fpgaminer1 will cut it in half, 2 down to a quarter, etc.02:48
Action: kristianpaul will try 5 later02:48
fpgaminerheh, yeah, that'll make it quite tiny :)02:48
kristianpaulthis value is later overwriten for the sha256_transform core, os another separate parameter?02:50
kristianpauland thats my last question :)02:50
kristianpaulI'm please you answer all this, i was holding a bit since past week :), plus i just get started to read about sha256 so still a way to understand all this !02:51
kristianpaulah yes it is derived from there02:52
kristianpaultought i need to understand that "ffset from the nonce"02:52
fpgaminerYou mean the LOOP parameter? Yeah that just defines how much to divide the pipeline by using 2**LOOP_LOG202:52
fpgaminerEach setting of LOOP_LOG2 will result in a pipeline with a different length, which means that there is a different delay between the nonces going into the core, and the results coming out. GOLDEN_NONCE_OFFSET adjusts for that so that "Golden Nonces" returned by the core represent the nonce that went into the core to generate the successful hash.02:54
fpgaminerIn other words, the data coming out of the mining core will always lag behind the data coming in. So when we want to report successful hashes to the outside world, we need to subtract the pipeline length.02:58
kristianpaulYes, a bit slow but small pipe so less fpga resources :)02:59
wolfspraulfpgaminer: are your altera sources uploaded somwhere?02:59
kristianpaulthat the only thing matters me now (fit :~))02:59
kristianpaulwolfspraul: github?02:59
fpgaminerwolfspraul: For my Milkymist port?03:00
fpgaminerwolfspraul: https://github.com/progranism/Open-Source-System-on-Chip-Experiment03:00
wolfsprauloh nice, I didn't know that link yet03:01
wolfspraulfpgaminer: thanks!03:01
wolfspraulso if anybody wants to try Milkymist on an Altera FPGA, we can point them that way?03:01
cladamw(audio path varistor candidate) AVR-M1005C080MTACB, Clamping Voltage:8V; Voltage Rating DC:5.5V http://search.digikey.com/us/en/products/AVR-M1005C080MTACB/445-2559-1-ND/93122703:04
fpgaminerwolfspraul: It's mostly my own experimentation taking pieces of Milkymist and getting them running on Altera, but in the long run I'll try to reach full parity with Milkymist.03:05
fpgaminerAltera devkits like the DE2-115 have everything except the MIDI inputs I think, so I can probably get pretty close to a full Milkymist port.03:06
kristianpaulbtw no minimac?03:07
fpgaminerkristianpaul: Haven't pushed to github in a few days. Code on my machine has minimac203:08
fpgaminerI spent a day trying to get the timing constraints to work for my devkit's PHY :/03:09
kristianpaulyeah minimac have some clock domains to deal with..03:10
fpgaminerNo kidding03:11
fpgaminerThe 88E1111 phy is supposed to hang clock shifting on its own if you set the proper register03:12
fpgaminerbut it wasn't working at 100Mbps; probably only works for 1000Mbps. So I just threw my hands in the air, shifted the clock by 90 degrees with a PLL, and called it a day.03:12
cladamwour M1R4 audio codec has AVDD rough 4.3V analog supply, with its recommend operating AVDD + 10% AVDD = 4.73V, within digi-key, we can sorting a varistor w/ 5.5V maximum, and 33pF@1KHz, 1 Vrms input, so this capacitance can let us reduce another extra 47pF on each audio path.03:14
kristianpaulfpgaminer: about kintex had you seen this http://www.xilinx.com/products/boards-and-kits/AES-K7DSP-325T-G.htm ?03:23
wpwrakcladamw: a few pf are good for filtering rf :)03:25
cladamwwpwrak, firstly i checked this: http://industrial.panasonic.com/www-data/pdf/AWC0000/AWC0000CE2.pdf03:27
cladamwthere's two catacories: high speed and low speed, so followed 'low speed' to search.03:28
cladamwbut digi-key didn't have that EZJP0V080DA, 33pF; so searched another brand AVR candidate.03:29
fpgaminerkristianpaul: Oh boy! They give a $1 discount if you buy over 100!!!03:29
wolfspraulfpgaminer: ah you are still there. Can I forward your HDMI comments you sent to me by mail to the milkymist list or the channel here?03:30
wpwrakcladamw: panasonic are rather generous: "dc voltage lines/high speed signal lines". seems universal :)03:31
cladamwwpwrak, we don't need to use much few capacitance @ low speed i think, regarding to panasonic introduction, we can select a 33pF, how do you think?03:31
wpwrak33 pF sounds fine to me03:31
cladamwwpwrak, yes, but scrolling down to see low speed, yeah !03:31
cladamwso i selected a compatible AVR in digi-key.03:31
wpwrakif you can find one with higher capacitance, maybe it can even act as a proper RF filter cap03:31
wolfspraulgotta run, bbiab03:33
cladamwwpwrak, want to more like 47pF?03:34
wpwrakmore like 220 pF, i think :)03:36
fpgaminerwolfspraul: Sure ... just don't take anything I say as authoritative :P03:36
fpgaminerI'm not exactly Silicon Image :P03:36
wpwrakah no, you're right. 47 pF :)03:37
wpwrakaccording to what i wrote :)  http://lists.milkymist.org/pipermail/devel-milkymist.org/2012-January/002583.html03:38
cladamwwpwrak, yuh... otherwise you're doing a bandwidth filter. ;-)03:38
cladamwwpwrak, yes, but the capacitance seems having rules on relying to varistor voltage and dc ratiing, so check like this: http://www.tdk.co.jp/tefe02/e9c11_avr.pdf03:40
cladamwalthough there's 40pF in 1005type (i.e. 0402 package) so according to WM9707 recommends spec. we should stick to a varitor voltage on 8V or 6.8V >= 4.73V (AVDD + 10%*AVDD),03:44
wpwrakhmm, capacitance goes up > 100 MHz. not much we can do about it, it seems03:44
wpwrakwell, except picking an ultra-low-capcacitance varistor that will be good up to 1 GHz03:45
wpwrakbut also 47 pF should serve us until ~300 MHz03:45
wpwrakso it should be fine at least for FM radio03:45
cladamwand also 'maximum continous voltage(rated voltage)' to 5.5V seems meet ours,03:46
cladamwoah~ yeah..a 47pF ~ reaching to FM. good analysis.03:46
cladamwwpwrak, so how do you think that sticking to p/n:  AVR-M1005C080MTACB ? or search more candidate ?03:49
wpwrakyeah, to me it look okay. we should check with joerg, though.03:52
cladamwwpwrak, okay.03:52
cladamwwpwrak, EZJP0V080GA, good ESD suppressed waveform: http://industrial.panasonic.com/www-data/pdf/AWC0000/AWC0000PE4.pdf03:55
wpwrakyeah, it just eats it :)03:58
cladamwwpwrak, I'll reply last time email & include joerg to check his idea this afternoon. ;-)04:02
wpwrakperfect :)04:04
kristianpauldvdk, your gforth port what c library is going to use?04:37
lekernelfpgaminer: hi08:41
lekerneltry this: https://github.com/milkymist/milkymist-ng08:41
fpgaminerlekernel: Is that an implementation of Milkymist One using migen?09:01
lekernelbut still incomplete09:29
Fallenoulekernel: so you fixed the sub-word stores ?10:09
Fallenoucool !10:15
lekernelhey, I can compile all of libbase with clang now10:38
lekerneleven inline assembly works10:39
Fallenouis it custom clang ?10:41
Fallenouor official debian squeeze packet10:41
GitHub99[llvm-lm32] sbourdeauducq pushed 1 new commit to master: http://git.io/l1xCDw10:42
GitHub99[llvm-lm32/master] Fix cmake build system for Mico32 - Sebastien Bourdeauducq10:42
lekernelit's the clang on our github10:42
lekernelnothing is merged yet10:42
lekernelyay, got a small "BIOS" to compile and link10:52
lekerneland it works :)10:53
lekernelgcc's end is soon, I guess10:53
Fallenouyou have a working uart with $displays() in milkymist-ng ?10:57
lekernelI have a working UART, but nothing in simulation yet10:58
Fallenouok it's on fpga10:58
GitHub197[milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/Eo_-Mw11:58
GitHub197[milkymist-ng/master] software: fix size_t and ptrdiff_t - Sebastien Bourdeauducq11:58
GitHub197[milkymist-ng/master] software: use the Clang/LLVM compiler - Sebastien Bourdeauducq11:58
GitHub26[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/3eOOgg12:07
GitHub26[milkymist-ng/master] software: enable -Wmissing-prototypes - Sebastien Bourdeauducq12:07
stekernI'm a bit confused, looking at the datasheet for the ddr sdram I see that there should be one cycle from we going low to dqs going high, but when running simulations on hpdmc, I see two cycles between we_n and dqs13:16
stekernfeels like I have misunderstood/missed something13:16
GitHub80[milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/qEgbYA13:18
GitHub80[milkymist-ng/master] uart: RX support - Sebastien Bourdeauducq13:18
GitHub80[milkymist-ng/master] software: UART RX demo - Sebastien Bourdeauducq13:18
lekernelDQS is asynchronous, so "two cycles" isn't very accurate13:19
stekernyes ofcourse, but I mean in the datasheet, tdqss(min) is < two cycles13:21
stekernnot min13:22
lekernelcan you post a screenshot?13:23
lekerneland note that WE is sampled by the DRAM on the rising edge of the clock13:24
lekernelso in simulations, WE is actually going low about one cycle before the DRAM samples it13:25
lekernelbut probably you already know that13:26
stekernlet's not rule out anything, as I said, I might well have misunderstood something13:27
stekernwait, I'll get a screenshot for you13:28
lekernelyes, DQS goes high exactly one cycle after the DRAM registers the write command13:36
lekernelwhich is in the middle of the DQS spec (IIRC)13:36
lekernelverilog simulations can be confusing at times... remember that signal transitions happen *after* clock edges and on a clock edge, the value immediately *before* the edge is registered13:37
lekernel(rising edges usually)13:37
stekernyes, the problem is that we_n changes 100ns before sdram_clk_p13:39
stekern(although that could be a problem in my sim setup)13:39
lekernelwe_n changes synchronously with the clock, you should only have delta delay differences (the latter are not shown in gtkwave)13:40
lekerneland 100ns looks like a lot of time at the speed the clock is running :)13:40
stekernsorry, that should have been 100ps ;)13:47
GitHub194[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/LzsiNw14:08
GitHub194[milkymist-ng/master] software: shell from original BIOS - Sebastien Bourdeauducq14:08
GitHub131[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/x5aIaw14:18
GitHub131[milkymist-ng/master] libbase: blocking UART write if IRQs are enabled - Sebastien Bourdeauducq14:18
stekernok, I have the same delay between sys_clk and sdram_clk_p, that probably explains it14:28
lekernelah, that could be inside the ODDR2s?14:29
lekernelnote that, in real life, the I/Os also have delays, which (hopefully) compensate for that of the ODDR2, with some margins14:30
stekernyes, sure, I'm pretty sure this is a simulation issue otherwise I wouldn't expect it to work at all14:31
stekernyes, it's the ODDR2s that generate that delay14:37
Action: lekernel is planning to submit a Migen paper to the Stockholm event17:23
FallenouMMU starts to work19:27
Fallenoumemory loads seem to be working :)19:28
Fallenouat least it worked once :p19:28
whitequarkoh, someone's working at MMU for M1? cool19:29
FallenouIt's gonna be tricky for memory stores19:32
Fallenousince LM32 caches are write through19:32
FallenouTherefore it simultaneously writes to Data bus *and* to Dcache19:33
wpwrakseems that you need to pipeline that19:36
Fallenouit's a 1 clock cycle operation19:38
FallenouI will try not to add latency19:39
wpwrakis memory write latency a problem, if pipelined ?19:40
Fallenouthe thing is that ATM the DTLB is implemented in lm32_dcache.v module19:41
Fallenouand in case of stores (write through) it goes directly on D_ADR_O lines from lm32_load_stores.v19:41
Fallenou(and simultaneously to lm32_dcache to update cache line where it can be handled by DTLB)19:42
wpwrakyeah, i was thinking of potential conflicts when going from WT to WB19:43
wpwrakthere could be some, it the memory interface is saturated and you don't want to add a delay in that case19:43
FallenouI will have to add some code to lm32_load_store_unit.v too, in order not to put the virtual address on D_ADR_O in case of mem stores, and not adding a 1-cycle dtlb lookup latency19:43
wpwraki.e., if you have a delayed write followed by a lot of reads, the reads could starve the write if they're prioritized19:44
FallenouI will try not to delay any write19:44
Fallenouto keep the same lm32 timings19:44
Fallenouthe less timing changes I have, the less bugs I can introduce19:45
wpwrakdo you can translate virt->phys in the same cycle ?19:45
wpwrak(no changes) yeah :)19:45
Fallenouyep the lookup virt->phy is 1 cycle19:45
Fallenouso if I have the address presented the cycle before it has to be used, I can do the lookup for free19:45
wpwrakand do you have the address one cycle before the write ?19:46
Fallenouthis I haven't looked yet :)19:46
FallenouI just saw the first load work properly19:47
wpwrakhehe :)19:48
wpwrakthe first step is usually the hardest L(19:48
Fallenouyep :)20:07
FallenouI just realized it only works if physical address is already cached20:08
Fallenoudamn 'X' state20:08
Fallenouthey are almost everywhere20:08
Fallenouand it fucks simulation up sometimes20:09
Fallenoueven if it does not exist in a real fpga20:09
Fallenouin simulation, non initialized sram contains "XXXXX" and not "0000" which makes some code fail :/20:09
Fallenoulet's initialize it20:10
ThihiHmm, so is ther anything about the milkymist project (software & hardware) which isn't open source?22:03
wpwrakthe synthesis tools ?22:04
larscthe FPGA itself is not22:04
kristianpaulthe FPGA fabbing process* i think22:11
wpwrakalso some of the underlying physics22:12
wpwrakmuch of them has been reverse-engineered, though22:12
larsci've heard you can get faked universes in china these days ;)22:25
dvdkjust tried to make qemu-lm32 work.  segfaults on me :/23:03
dvdkinstalled as described here: http://milkymist.org/wiki/index.php?title=Using_QEMU23:03
dvdk(used git checkout 12d4... instead of 'git revert', 'git revert' gives errors)23:03
dvdk git checkout 12d4536f7d911b6d87a766ad7300482ea663cea223:03
dvdk./configure --target-list="lm32-softmmu" --enable-sdl && make23:03
dvdksudo make install23:03
dvdkwget http://www.milkymist.org/updates/current/bios.bin -O mmone-bios.bin23:03
dvdk  /usr/local/bin/qemu-system-lm32 -M milkymist -bios ./mmone-bios.bin -nographic23:04
dvdkfrom gdb:23:04
dvdkProgram received signal SIGSEGV, Segmentation fault.23:04
dvdk0x00007ffff5ca3a87 in pthread_cond_broadcast@@GLIBC_2.3.2 ()23:04
dvdk   from /lib/libpthread.so.023:04
dvdkany ideas?23:04
dvdkjust attempting to load gforth-ec into mm1 via netboot23:16
dvdknow, at the bios prompt typing 'netboot' requests firmware from hard-coded IP  is there a way to change that address?23:16
fpgaminerIt's a define in the sourcecode23:19
dvdkhmm :/23:20
Action: dvdk will try to use serialboot/flterm23:20
dvdkok, flterm seems to do the job.  does it pass-through serial output after booting the device, or do I have to launch another gtk-term to see anything?23:27
dvdkBTW does the mm1 board have some (hidden?) reset button?23:27
dvdkcurrently pulling the DC cable for reset.  hope the receptabel survives that23:28
dvdkcan I use the jtag interface via urjtag to reset the lm32 CPU (or the whole board for that matter)?23:49
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