#milkymist IRC log for Monday, 2012-02-06

dvdklook here: www.iwar.org.uk/comsec/resources/cipher/sha256-384-512.pdf00:00
dvdkone block of sha256 takes 64 rounds (i.e. 64 cycles), and 8 registers a 32 bits.00:01
kristianpaulah yes also crypto stuff :)00:01
dvdkfor mining you need 2 blocks per hash, i.e. 128 rounds.  so at 128 MHz you're at 1Mhash/sec, that's too low.00:01
dvdkso I guess people instantiate multiple hash-algos that work in parallel.00:02
kristianpaulah, i havent check hash core lets hace a quick look00:02
dvdkso, try to scale the design down.00:02
dvdki.e. reduce number of instantiated hashers.00:02
dvdkthe spartan6 in mm1 is a pretty small model.00:02
kristianpaulyeah..00:03
kristianpauli tried lowering a LOOP_LOG2 paramer i found00:03
kristianpaulfrom some forums and the fpgaminer core00:03
kristianpaulthis is derivated from ztex00:03
Action: dvdk thinks people who run fpgaminer use *much* larger fpgas.00:03
kristianpaulthe cheat also00:04
kristianpauluse chipscore to read results i think00:04
kristianpauls/the/they00:04
kristianpaulhttps://github.com/ngzhang/Icarus/tree/master/FPGA_project/Src is nice because implement serial comunciation00:05
kristianpauldvdk: larger yes but there is people who oen atlys boards wich is quite similar to M100:06
kristianpauls/oen/own00:07
cladamwwpwrak, do you think out a way that we can do design verification on DVI-I differential pairs on rc3 firstly?02:32
wolfspraulcladamw: good morning! :-)02:33
cladamwcan rc3 be made it possible?02:33
cladamwwolfspraul, good morning . :)02:33
cladamwwpwrak, i knew it was bad that current wires from J21 came from bank1 not bank202:34
cladamwthe TMDS signals do not supported in bank102:35
wpwrakoh, didn't know there were more constraints. when i asked if there were other "special" features besides the clock, nobody spoke up :-(02:37
wpwrakanyway, seems that we'll have to try our luck without dvi design testing02:38
cladamwhmm...i did also feel that way ! :(02:41
cladamwwpwrak, btw have you seen this thread already? http://lists.milkymist.org/pipermail/devel-milkymist.org/2011-October/001966.html02:42
wpwrakyes, i've seen it. do you expect any specific reaction from me ? i don't know much about dvi, so it's basically "aha, interesting" from me :)02:50
cladamwwpwrak, phew~ i see. I've be noticed myself that hopefully and to be carefully known well background knowledge behind dvi-i, there's 50 ohm in series on PMODA/JA for the "direct connection" example: http://www.digilentinc.com/Data/Products/ATLYS/Atlys_C2_sch.pdf03:13
wpwrakah, you didn't have that yet. i see03:21
cladamwand compared to its HDMI OUT(J2) without need 50 ohm. The 50 ohm resistors which is designed for TMDS received to fpga after checked http://www.xilinx.com/support/documentation/user_guides/ug381.pdf03:22
cladamwthe 50 ohm seems no need while act as receiver which differ to we act as a transmitter03:22
wpwrakmaybe the termination for HDMI is already in the transceiver chip03:23
cladamwbut from Atlys, i don't fully understand why there's a TI chip there.03:23
cladamwso my question is : would it as a must to pull fpga wire connection via buffer.03:24
wpwrakug381 doesn't make sense :)03:25
wpwrak"The TMDS standard requires external 50 resistor pull-ups to 3.3V on inputs."03:25
wpwrak50 Ohm **PULL-UP** ? yeah, sure ;-)03:26
wpwrakah wait ... if they're combined with series resistors on output, that would make sense03:27
wpwrakokay, it does make sense :)03:27
wpwrakand then it's also logical that the outputs would have to have 50 Ohm series resistors03:28
cladamwyes, but which they are describing for tmds receiver not like our output goal, agreed?03:29
wpwrakhmm. figure 1-19 doesn't have output resistors03:30
cladamwcorrect03:30
cladamwalso i strongle figured that we might misunderstand the distance vs skin effect, check my log: http://en.qi-hardware.com/mmlogs/milkymist_2011-12-08.log.html#t12:4803:31
wpwrakso i don't know who is right. xilinx or digilent03:31
wpwrakmaybe PMODA is something else that just looks like HDMI ?03:31
wpwrakthe others say HDMI IN/OUT03:32
cladamwnot sure, but we can't do 'direct connection' under things we don't really know.03:32
cladamwyes,03:32
wpwrakyou can add 0Rs ;-)03:32
cladamwbut ours is much close to act as a like HDMI OUT, correct?03:33
cladamwso my question is still : why add buffer?03:33
wpwraktheir HDMI out has a special chip. so that doesn't tell us anything.03:33
cladamwdid we miss important specifications behind TMDS ?03:33
wpwrakmaybe protection. maybe it produces a cleaner/stronger/etc. signal ?03:33
cladamwso please read : page 2 from http://www.pericom.com/pdf/applications/AN204.pdf03:34
wolfspraulcladamw: we don't need the TI buffer chip03:35
wolfspraulthat was discussed several times already03:35
cladamwwolfspraul, wait03:35
cladamwi am confirming and discussing with Werner about high frequency behavious to know why.03:35
wpwrak(270-280 mil) yeah, seems a little weird :)03:36
cladamwwpwrak, from that pericom data which is MUCH Importatce that we need buffer !03:36
cladamwso i double checked http://en.qi-hardware.com/mmlogs/milkymist_2011-12-08.log.html#t10:0903:37
cladamwwhen I reviewed that.03:37
cladamwso we need very sure that (270-280 mil) which already against our current planned distance from fpga to dvi conector03:38
cladamwso I need to SPEAK up this in advance, at least we really fully understand the content of pericom and schematic example from ATLYS.03:40
wpwraki couldn't make sense of these design parameters back then and i can't now :-(03:42
wpwrakpericom specify nearly impossible requirements03:42
wolfspraulwe don't need the buffer chip03:42
wolfspraulit was discussed 5+ times03:42
wpwrakexisting boards place things at large distances apparently without problems03:42
wolfspraulyep03:42
wpwrakso there's something that doesn't add up03:43
wolfsprauleverybody tries to sell their stuff03:43
wolfspraulwhat's better than selling into fear :-)03:43
wpwrakmaybe pericom are specifying for excessive data rates or such03:43
wpwrak;-)03:43
cladamwwpwrak, no problem, take you r time. i just feel pericom has that important data to know what idea behind it, and would it be related to why there's buffer added in ATLYS?03:43
wolfspraulthere's a buffer on atlys because TI paid them to add it03:43
wolfsprauland it seems to work :-)03:43
wolfspraulnow you think you need it too :-)03:43
wpwrakcladamw: it's not a question of time but of dvi design experience :)03:44
wolfspraulseriously the buffer on the atlys board is really there because TI paid03:44
wolfspraulin fact there are 2 outputs on that board, one with the buffer and one without03:45
wolfspraulseems atlys didn't want to let TI take hostage of their customers entirely... :-)03:45
wolfspraulif we need the buffer chip, we have to find out from hard requirements, not from fear03:45
wpwrakdimissing buffers just a FUD seems a bit too simple :)03:45
wolfsprauland for the time being we are aware of existing boards that indicate that we do not need the chip03:46
wolfspraulI don't03:46
wpwrakfrequency ranges would be something i could accept as an explanation03:46
wpwrakor cable length03:46
cladamwwpwrak, i am more focusing on pericom theory on its analysis. not saying if we must add buffer or not.03:46
wolfspraulbut we had this discussion 5 times03:46
wolfspraulresolution and bandwidth can go very high03:46
wolfspraulit's not binary03:46
wolfspraulit's not like you always need the chip, or never03:46
wolfspraulbut most likely on m1 r4, the buffer chip would serve no purpose03:46
wolfspraulbut you can clearly see the power of devel boards here, and that it makes sense to have your chips on them :-)03:47
cladamwatlys added buffer is for htmi extendable cable03:47
wolfspraulit's because TI paid03:47
cladamwbut for ourside, surely the dvi-i extendable cable is still be used for m1.03:48
wolfspraulI believe that (in)famous atlys board has a second hdmi without buffer chip. that's fair enough, so the (developer) users of that board can compare the actual performance and need of the TI buffer chip.03:49
wolfspraulI am quite certain that we don't need the buffer chip on m1 r4, or rather that it would not serve any meaningful purpose.03:49
wolfspraulafter this having been discussed several times03:49
wpwrakwhat's the maximum length of a DVI cable anyway ? maybe that's the thing. monitor right next to the computer vs. projector at the other side of the room03:50
wolfspraulI think stekern pointed to some boards that are happy without it, up to resolutions that are so high that I would jump up and down in joy if m1 can get there...03:50
cladamwif TI buffer is designed for buffering TMDS signals, why in our side, as we still need dvi cable connected to dvi monitor, would it be still act well with long cable?03:50
wolfspraulwpwrak: but you bet there are cables with built-in buffers/signal improvement ics or whatever as well03:50
wolfspraulcladamw: we have to find out03:50
wolfspraulbut we start without the TI chip03:51
wpwrakwolfspraul: $$$ cables :)03:51
wolfspraulyes but we cannot just add chips because we know nothing03:51
cladamwso please let us be carefullu on this.03:51
wolfspraulbut we can make the first step, even if we know nothing03:51
wolfspraulcladamw: the chip is not needed03:51
wolfspraulit was discussed many times03:51
wpwrakso, m1r4 probably only with short dvi cables, m1r5 with unlimited ones ;-)03:51
wolfspraulmaybe03:52
cladamwif dvi cable bounded with buffer inside, then safe, but which is not common i think.03:52
wolfspraulsure sure03:52
wolfspraulyou guys can discuss03:52
wolfspraul:-)03:52
wpwrakif you need an active cable for anything, that means you're desperate. prices are according ;-)03:52
wolfspraulthe chip is not needed03:52
wolfspraulthere's a link somewhere to a board or boards and the resolutions achieved without buffer03:53
wolfspraulwhich doesn't mean we will see the same performance on m1 r4 of course03:53
cladamwboard to board without buffer I can agreed, but now our case is board to long dvi cable.03:54
wolfspraulwe don't need the buffer03:54
wolfspraulbut I do suggest that we make the first run of r4 only 6-10 pc or so03:55
wolfspraulaccelerate that03:55
wolfspraulhttp://rubidium.dyndns.org/pipermail/fpga-synth/2011-April/001667.html03:57
wolfspraullet me paste a little from that nice mail... :-)03:57
wolfspraulsince you torture me, I torture back03:57
wolfspraul"Contrary to what I thougt it appears that03:57
wolfspraulthe HDMI buffer chip doesn't play a role in getting the "too fast" signals03:57
wolfspraulout.03:57
wolfspraulThe 193MHz pixel clock was actually producing a bit cleaner picture03:58
wolfspraulwith the direct output (to be fair, that exceeds the spec of the HDMI buffer03:58
wolfspraulchip by quite some margin).03:58
wolfspraul---03:58
wolfsprauldoes this apply to m1 r4? I don't know03:58
wolfspraulbut I feel quite confident that we should do m1 r4 without the buffer chip, and apply everything else to the best of our knowledge in terms of the wires, signal integrity, etc.03:59
wpwrakyeah, considering that this isn't the only unknown about dvi, probably a reasonable choice04:02
wolfspraulcladamw: we were told from people that designed/made hdmi boards before that we should not need the TI buffer chip04:05
wolfspraulI think that's enough04:05
wolfspraulso let's focus on everything else ;-)04:05
wolfspraulwe may still discover the value/need of that chip later, but the best way to that discovery is to first try without it04:05
wolfspraulotherwise I don't see what next step you propose :-)04:05
cladamwwolfspraul, well fine that link, if you think 'one' link can prove unconcerned tasks, i just didn't want dvi-i connector with failure in the end then go R5.04:11
wolfspraulI carefully thought about this [buffer chip]04:11
wolfspraulI think about the different paths04:12
wolfspraulwhich actual path do you propose?04:12
wolfspraulI am not saying I know what will work04:12
wolfspraulbut i am pretty sure that we should first make R4 without buffer chip04:12
wolfsprauland do everything else as best as we can on signal integrity04:12
wolfsprauleven there we have some exceptions because we don't want to move existing pins, or even rotate the entire s-604:12
wolfspraulthose are all options we theoretically have, but choose not to do because we "think" they are not needed04:13
wolfspraulI do propose that the first SMT run of R4 be only 6-10 pieces though04:13
wolfspraulamong other things because of DVI signal integrity04:13
wolfspraulthat should make you feel better, no? :-)04:13
cladamwi do have no actually path i can do now, just liked i also got 'one' link of data, then i spoke up.04:13
wolfsprauloh yes04:13
wolfspraulthat is very good!04:13
wolfspraulwe may be desperately looking for that link in a few weeks :-)04:14
wpwrakit may make sense to consider the possibility of adding such a buffer chip in the future when doing the layout. i.e., to make sure the DVI area isn't overly crowded04:14
cladamwso what current channel we have now in here, i just wanted to rise up this again surely i don't have alternative solutions.04:15
wolfspraulwpwrak: such a requirements would only confuse layout04:16
wolfspraulif such a chip is to be added, it's a layout change anyway, and can be looked at then04:17
wolfspraulthe goal now is to make no signal integrity mistakes in R404:17
wolfspraulnot to prepare for R504:17
wolfspraulif anything I think the issue of 'no reordering of existing pins' or 'rotate s-6' or 'move dvi-i connector to other side' could make more sense to think about04:18
wolfspraulshould we move the dvi-i connector to another side?04:18
wolfspraulthat'd be a massive layout change...04:18
wpwrak(rotate the fpga) yes, if it comes to that, it gets messy04:18
wolfspraulbut the side panels of the case change anyway, from the mechanical side it's manageable04:19
wolfspraulI am not proposing that btw04:19
wolfspraulbut if the "buffer chip" discussion comes up, there is no reason to not also discuss rotating the s-6 or moving the dvi connector to another side...04:19
wolfspraulhow do we know that that wouldn't help more? -> we don't04:19
wolfspraulso I think best path is shortest path to actual (small) R4 run04:20
wpwrak(move dvi elsewhere) hmm, sounds messy04:20
wolfspraulmake only small modifications if possible04:20
wpwrakyou'd have to swap with midi and/or dmx04:20
wpwrakone issue is that the balls will be about 7 cm from the connector. that's ten pericoms (the pericom being a unit of paranoid distance)04:21
cladamwi was not to convince or  torture, since as engineering thoughts, just don't want it being failed in R4 in the end. Compromising in determined by route or rotating s-6 decision is not most topic we want now. I just don't have more confidence when i digged-into seeing pericom & atlys info, i suddently have no confidence at all.04:22
wolfspraulI think we should not do that04:22
wolfspraulbut as I said a few times now, I do think the first R4 smt run should only make 6-10 pieces04:22
cladamwwpwrak, yes, ten times04:22
wolfspraulwe understand the industry currently works on quad-HD and stuff...04:22
cladamwso I want more people like wpwrak can spend some times to dig-into...i am enbarrassing though. :(04:23
wolfspraulwe do that after we have made some R4 boards04:23
wolfspraul(without buffer chip)04:23
wolfspraulthat's the most economical way04:24
cladamwwolfspraul, okay04:24
wolfspraulcladamw: did you see what i wrote about size of initial r4 smt run?04:24
wolfspraulwe are making a lot of (good) changes04:25
wolfsprauland I also want to accelerate those changes, not get stuck worrying forever04:25
wolfspraulbut then in return, I think we should only make a few boards first04:25
wolfspraul6 or 8 or so04:25
cladamwnow you 6 - 1004:25
wolfspraulif they are fine, they can be built into full products04:25
wolfspraulwe can make more PCBs right away, but a smaller SMT first04:25
wolfspraulit's just an idea how to accelerate04:26
wolfsprauland take some stress from you :-)04:26
wolfspraulif those 6-10 boards don't work, it's all on me :-)04:26
wolfspraul(or some part of them doesn't work...)04:26
wolfspraulcladamw: if we are lucky, the layout people have routed digital video before? maybe they have some feedback as well?04:27
cladamwwolfspraul, sure, need to get feedback from them, but not now. since we've not finished all else details, so i don't want to bother them now.04:29
wolfspraulsure04:29
wolfspraulhave to run, bbl04:32
GitHub92[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/1a86f26a66a357dce548a279b22badf6ab2d044310:24
GitHub92[migen/master] bank/csrgen: use enumerate - Sebastien Bourdeauducq10:24
cladamw(2 pins header) wpwrak J25's two +5V pins connects to a 2x1 header without jumper in default: http://downloads.qi-hardware.com/people/adam/m1/tmp/m1r4/FPGA_J25_header_20120206.pdf12:33
cladamwdo you meant like in this way? did i misunderstand?12:33
cladamwI drew J25 besides J21.12:34
GitHub90[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/f3ddfffc470b0a59e9d02b7b9bc63f7f3da5e9ba13:01
GitHub90[migen/master] bank: refactoring - Sebastien Bourdeauducq13:01
GitHub146[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/3a2a0c4dd80c40cd34b783113c058f5047e6e79315:21
GitHub146[migen/master] bank: support registers larger than the bus word width - Sebastien Bourdeauducq15:21
GitHub37[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/fcd6583cbbcc366c16e9bc1038dc305aaf323c7516:45
GitHub37[migen/master] bank: event manager - Sebastien Bourdeauducq16:45
GitHub11[milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/1EZL1Q16:51
GitHub11[milkymist-ng/master] UART: use new bank API and event manager - Sebastien Bourdeauducq16:51
GitHub11[milkymist-ng/master] top: connect UART IRQ - Sebastien Bourdeauducq16:51
GitHub187[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/kZ1p1Q16:59
GitHub187[milkymist-ng/master] software: use new UART - Sebastien Bourdeauducq16:59
GitHub129[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/1eb348c573dfb68c67ed09445e5fdb5f524ac8b617:12
GitHub129[migen/master] fhdl: do not attempt slicing non-array signals to keep Verilog happy - Sebastien Bourdeauducq17:12
lekernel$ cat lenovo_laptops_are_shit.sh17:13
lekernel#!/bin/sh17:13
lekernelwhile true; do17:13
lekernel        killall -STOP par17:13
lekernel        killall -STOP map17:13
lekernel        sleep 117:13
lekernel        killall -CONT par17:13
lekernel        killall -CONT map17:13
lekernel        sleep 117:13
lekerneldone17:13
lekernelan alternative is to put that piece of crappy hardware outside where it's -16C ...17:14
larsci7?17:16
lekernelcore2 duo T930017:17
lekernelwith an obviously lousy cooling system17:17
wpwrak;-))17:25
GitHub97[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/47883675dbf71dc98814930330e7e2b68b56c80817:49
GitHub97[migen/master] bus/wishbone2csr: truncate WB data - Sebastien Bourdeauducq17:49
lekernelFallenou: did you fix the RAM problems?18:07
Fallenouicache and dcache are now working fine18:14
Fallenouicache pb was solved by your commit about WE18:14
Fallenoudcache solved by initializing register 0 in lm32_dp_ram.v18:15
Fallenoufunny thing is that clogb2(4096)  == 13 for isim18:16
Fallenoui'm using clogb2_v1 now18:17
Fallenoui wonder if this bug screws up anything else18:18
lekernelI have problems with < 32-bit accesses atm18:24
lekernelin sram18:24
lekernelprobably a typo somewhere ...18:24
Fallenoui didn't check all the values btw18:25
Fallenoujust that the pattern i see in the wave form is correct18:25
Fallenoubut i have not seen unexplainable values18:25
Fallenoui just have a loop with a few lb18:25
Fallenouand nops18:25
Fallenouatm18:25
lekernelreading bytes works, it's only with writing bytes or 16-bit words that there are problems18:28
Fallenouoh ok18:29
Fallenouthats why I didn't see it18:30
Fallenouomg your script18:48
Action: Fallenou is not in such a bad position with his mac book pro virtualizing a debian18:48
Fallenounow I understand why they put clogb2()-1 everywhere18:50
Fallenoubecause their log2 is log2 + 118:50
Fallenoucrazy18:50
sionneaudamn, freenode server maintenance20:26
dvdkhuh, found an error in the gcc toolchain's disassembler?  or do i just need more coffee:21:24
dvdkprintf '\x4f\x00\xff\xff' > /tmp/opcode && /opt/rtems-4.11/bin/lm32-rtems4.11-objdump  -EB -b binary -m lm32  -D /tmp/opcode21:25
dvdkthis prints 0:4f 00 ff ff bge r24,r0,0xfffffffc21:25
dvdkbut according to the LatticeMico32 Reference Manual, it should quite clearly be (bge r0,r24,...)21:25
dvdki.e. order of registers is displayed wrongly21:25
dvdkok, echo 'bge r24,r0,-4' > /tmp/test.asm, assembling, then disassembling gives identity.21:29
dvdkso i guess the manual is wrong!?21:29
Fallenoulekernel: http://sionneau.net/mmu/ :-)21:46
Fallenouthis sets up a DTLB entry to map 0x1000 to 0x0000 and then reads from 0x100021:47
Fallenouoops this proves nothing21:48
Action: Fallenou shouting victory too soone21:48
Fallenousoon*21:48
kristianpaulgood :)21:49
Action: Fallenou needs to enlarge sram of the project21:50
Action: Fallenou needs several pages21:50
lekerneland wait until you get mmu schrödinbugs in the middle of linux kernel tests :-)21:56
Fallenoulekernel: why is sram0_wishbone_adr_i  10 bits wide ?21:56
larsclekernel: you can still blame linux for it21:57
Fallenouahah yep schrodinbugs ==)21:57
Fallenouok nevermind it's normal21:57
FallenouI was reading 4096 in megabytes ... it's in kilobytes21:58
dvdkcool, you already have a (working?) mmu for LM32?22:09
FallenouI thought it was starting to work22:19
Fallenoubut no, not yet :)22:19
Fallenoubut I'm quite done putting lm32 simulation in place, finish debugging the debug environment :)22:19
Fallenounow I can start working on debugging the mmu22:19
dvdkmilkymist moves forward at a pace that I can hardly follow :)22:20
Fallenouyes, there is a bunch of very productive people over here :)22:21
Fallenouit's quite amazing22:21
dvdkwrt debugging the debug environment, I'm currently trying to port gforth-ec over to LM32 to use as a debug "operating system".  Don't like to cross-compile&upload a hundred times just for testing a SoC components22:24
Action: kristianpaul dont like cross-compile either22:26
lekerneluploading is pretty fast with netboot and a script22:27
dvdklekernel: yeah, but then it looses state, whenever I upload :)22:28
Fallenougn8 !22:29
kristianpauln822:29
dvdkbtw looking at the bios sources it seems like it will load from flash first, before reverting to netboot?  need to write sth to flash to force netboot?22:29
kristianpauland set up netboot enviroment :)22:29
lekernelyou can press F8 during boot, and it will netboot22:30
lekernelalternatively you can erase FN from your flash so you don't have to press F8 every time (it'll only boot from network)22:30
dvdklekernel: ah cool, F8 is easy to remember.22:31
GitHub145[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/UGrWvQ22:45
GitHub145[milkymist-ng/master] sram: fix sub-word write - Sebastien Bourdeauducq22:45
Action: lekernel found a ACPI hack to double the speed of the fan. now it's noisy, but at least fpga compilations can run.23:11
wpwrakwhat will you do in summer ? move south ?23:22
GitHub110[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/DcnAVw23:42
GitHub110[milkymist-ng/master] software: interrupt driven UART working - Sebastien Bourdeauducq23:42
GitHub168[milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/3g70mg23:51
GitHub168[milkymist-ng/master] LM32: make IP read-only and interrupt lines level-sensitive - Sebastien Bourdeauducq23:51
GitHub168[milkymist-ng/master] software: remove unnecessary IRQ acks - Sebastien Bourdeauducq23:51
--- Tue Feb 7 201200:00

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